The Week in HPC Research

By Tiffany Trader

March 7, 2013

The top research stories of the week have been hand-selected from prominent journals and leading conference proceedings. Here’s another diverse set of items, including novel methods of data race detection; a comparison of predictive laws; a review of FPGA’s promise; GPU virtualization using PCI Direct pass-through; and an analysis of the Amazon Web Services High-IO platform.

Scalable Data Race Detection

A team of researchers from Berkeley Lab and the University of California Berkeley are investigating cutting-edge programming languages for HPC. These are languages that promote hybrid parallelism and shared memory abstractions using a global address space. It’s a programming style that is especially prone to data races that are difficult to detect, and prior work in the field has demonstrated 10X-100X slowdowns for non-scientific programs.

In a recent paper, the computer scientists present what they say is “the first complete implementation of data race detection at scale for UPC programs.” UPC stands for Unified Parallel C, an extension of the C programming language developed by the HPC community for large-scale parallel machines. The implementation used by the Berkeley-based team tracks local and global memory references in the program. It employs two methods for reducing overhead 1) hierarchical function and instruction level sampling; and 2) exploiting the runtime persistence of aliasing and locality specific to Partitioned Global Address Space applications.

Experiments show that the best results are attained when both techniques are used in tandem. “When applying the optimizations in conjunction our tool finds all previously known data races in our benchmark programs with at most 50% overhead,” the researchers state. “Furthermore, while previous results illustrate the benefits of function level sampling, our experiences show that this technique does not work for scientific programs: instruction sampling or a hybrid approach is required.”

Their work is published in the Proceedings of the 18th ACM SIGPLAN symposium on Principles and Practice of Parallel Programming.

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Predicting the Progress of Technology

A fascinating new study applies the scientific method to some of our most popular predictive models. A research team from MIT and the Santa Fe Institute compared several different approaches for predicting technological improvement – including Moore’s Law and Wright’s Law – to known cases of technological progress using past performance data from different industries.

Moore’s Law, theorized by Intel co-founder Gordon Moore in 1965, predicts that a chip’s transistor count will double every 18 months. In more general terms, it suggests that technologies advance exponentially with time. Wright’s Law was first formulated by Theodore Wright in 1936. Also called the Rule of Experience, it holds that progress increases with experience. Other alternative models were proposed by Goddard, Sinclair et al., and Nordhaus.

The study, which employed hindcasting, used a statistical model to rank the performance of the postulated laws. The comparison data came from a database on the cost and production of 62 different technologies. The expansive knowledge-base enabled researchers to test six different prediction principles against real-world data.

The results revealed that the law with the greatest accuracy was Wright’s Law, but Moore’s Law was a very close second. In fact, the laws themselves are more similar than previously realized.

“We discover a previously unobserved regularity that production tends to increase exponentially,” write the authors. “A combination of an exponential decrease in cost and an exponential increase in production would make Moore’s law and Wright’s law indistinguishable…. We show for the first time that these regularities are observed in data to such a degree that the performance of these two laws is nearly the same.”

“Our results show that technological progress is forecastable, with the square root of the logarithmic error growing linearly with the forecasting horizon at a typical rate of 2.5% per year,” they conclude.

The team includes Bela Nagy of the Santa Fe Institute, J. Doyne Farmer of the University of Oxford and the Santa Fe Institute, Quan Bui of St. John’s College in Santa Fe, NM, and Jessika E. Trancik of the Santa Fe Institute and MIT. Their findings are published in the online open-access journal PLOS ONE.

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FPGA Programming for the Masses

FPGAs (field programmable gate arrays) have been around for many years and show real potential for advancing HPC, but their popularity has been restricted because they are difficult to work with. This is the assertion of a group of researchers from the T.J. Watson Research Center. They argue that FPGAs won’t become mainstream until their various programmability challenges are addressed.

In a paper published last month in ACM Queue, the research team observes that there exists a spectrum of architectures, with general-purpose processors at one end and ASICs (application-specific integrated circuits) on the other. Architectures like PLDs (programmable logic devices), they argue, have that best-of-both-worlds potential in that they are closer to the hardware and can be reprogrammed. The most prominent PLD is in fact an FPGA.

The authors write:

FPGAs were long considered low-volume, low-density ASIC replacements. Following Moore’s law, however, FPGAs are getting denser and faster. Modern-day FPGAs can have up to 2 million logic cells, 68 Mbits of BRAM, more than 3,000 DSP slices, and up to 96 transceivers for implementing multigigabit communication channels. The latest FPGA families from Xilinx and Altera are more like an SoC (system-on-chip), mixing dual-core ARM processors with programmable logic on the same fabric. Coupled with higher device density and performance, FPGAs are quickly replacing ASICs and ASSPs (application-specific standard products) for implementing fixed function logic. Analysts expect the programmable IC (integrated circuit) market to reach the $10 billion mark by 2016.

The researchers note that “despite the advantages offered by FPGAs and their rapid growth, use of FPGA technology is restricted to a narrow segment of hardware programmers. The larger community of software programmers has stayed away from this technology, largely because of the challenges experienced by beginners trying to learn and use FPGAs.”

The rest of this excellent paper addresses the various challenges in detail and brings attention to the lack of support for device drivers, programming languages, and tools. The authors drive home the point that the community will only be able to leverage the benefits of FPGAs if the programming aspects are improved.

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GPU Virtualization using PCI Direct Pass-Through

The technical computing space has seen several trends develop over the past decade, among them are server virtualization, cloud computing and GPU computing. It’s clear that GPGPU computing has a role to play in HPC systems. Can these trends be combined? A research team from Chonbuk National University in South Korea has written a paper in the periodical Applied Mechanics and Materials, proposing exactly this. The investigate a method of GPU virtualization that exploits the GPU in a virtualized cloud computing environment.

The researchers claim their approach is different from previous work, which mostly reimplemented GPU programming APIs and virtual device drivers. Past research focused on sharing the GPU among virtual machines, which increased virtualization overhead. The paper describes an alternate method: the use of PCI direct pass-through.

“In our approach, bypassing virtual machine monitor layer with negligible overhead, the mechanism can achieve similar computation performance to bare-metal system and is transparent to the GPU programming APIs,” the authors write.

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Analysis of I/O Performance on AWS High I/O Platform

The HPC community is still exploring the potential of the cloud paradigm to discern the most suitable use cases. The pay-per-use basis of compute and storage resources is an attractive draw for researchers, but so is the illusion of limitless resources to tackle large-scale scientific workloads.

In the most recent edition of the Journal of Grid Computing, computer scientists from the Department of Electronics and Systems at the University of A Coruña in Spain evaluate the I/O storage subsystem on the Amazon EC2 platform, specifically the High I/O instance type, to determine its suitability for I/O-intensive applications. The High I/O instance type, released in July 2012, is backed by SSD and also provides high levels of CPU, memory and network performance.

The study looked at the low-level cloud storage devices available in Amazon EC2, ephemeral disks and Elastic Block Store (EBS) volumes, both on local and distributed file systems. It also assessed several I/O interfaces, notably POSIX, MPI-IO and HDF5, that are commonly employed by scientific workloads. The scalability of a representative parallel I/O code was also analyzed based on performance and cost.

As the results show, cloud storage devices have different performance characteristics and usage constraints. “Our comprehensive evaluation can help scientists to increase significantly (up to several times) the performance of I/O-intensive applications in Amazon EC2 cloud,” the researchers state. “An example of optimal configuration that can maximize I/O performance in this cloud is the use of a RAID 0 of 2 ephemeral disks, TCP with 9,000 bytes MTU, NFS async and MPI-IO on the High I/O instance type, which provides ephemeral disks backed by Solid State Drive (SSD) technology.”

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