NERSC Managers Shed Light on ‘Edison’

By Nicole Hemsoth

April 29, 2013

At the end of March, the Department of Energy’s National Energy Research Scientific Computing (NERSC) Center accepted the first phase of its new Cray Cascade system. Named Edison, the new machine is a Cray XC30 with 664 compute nodes and 10,624 cores. Each node has two eight-core Intel “Sandy Bridge” processors running at 2.6 GHz (16 cores per node), and has 64 GB of memory.

While the user environment on Edison is remarkably similar to that on Hopper, NERSC’s current main system, a number of new features and technologies are available on the Edison Phase I system, including the Cray Aries high speed interconnect, Hyper-Threading technology, the Sonexion storage system, and an external batch server. Once fully installed later in 2013, Edison will have a peak performance of more than 2 petaflop/s. The integrated storage system will have more than 6 petabytes (PB) of storage with an I/O bandwidth of 140 gigabytes (GB) per second.

Bucking the trend toward GPUs and hybrid architectures, Edison will use Intel processors exclusively. To find out the reasoning behind the design and deployment of Edison and what it means to NERSC’s 4,500 users, Jon Bashor of Berkeley Lab Computing Sciences spoke with NERSC Division Director Sudip Dosanjh, NERSC Systems Department Head Jeff Broughton and Advanced Technologies Group Leader Nick Wright.


Jon Bashor: First of all, how did the system come to be named Edison?

Jeff Broughton: At NERSC, we name our computers after famous scientists, like Hopper for Grace Hopper and Franklin for Benjamin Franklin. In this case, we were looking for someone iconic, someone who represented American team science. Thomas Edison was the obvious choice, especially for his work in the field of energy. His work had practical applications, and while NERSC supports mainly basic research, naming the system after Edison will be a constant reminder to consider the applied connotations of the science we support.

Bashor: When the procurement was announced in June 2012, the new system was described as delivering more than 2 petaflop/s peak performance, about twice that of Hopper. When other centers announce procurements, the new systems often provide an order of magnitude increase in performance. Is NERSC exiting the peak performance race?

JB: Although NERSC systems in the past have been highly ranked, NERSC has never been part of the peak performance “race.” We have always focused on the sustained performance of scientific applications as the basis for our procurements. For the most part, over the past 10 years, sustained performance has been a relatively constant fraction of peak performance. But with the move to GPUs and manycore systems, it has become increasingly difficult to maintain the traditional sustained/peak ratio. Getting users to move to these new architectures requires a major effort to port their applications.

As we transition to the path to exascale over the next decade, we think we can ask our 4,500 users to make the move to an entirely new class of architecture only once. We made a conscious decision that this is not the time for our users to make the transition and to let the architectures get sorted out before making that move. Our next system, now referred to as NERSC-8, will adopt one of the new energy-efficient architectures.

We are also seeing in our user community a big increase in data-intensive computing, with a focus on high throughput and single-node performance, so another goal was to provide a system that could meet the needs of data-intensive applications while continuing to support conventional HPC.

And we will continue to apply one of our unofficial benchmarks – the number of published research articles published by our users based on calculations performed at NERSC. We’ve averaged 1,500 per year for the past five years – another example of the sustained performance we are most interested in.

Bashor: Edison will be one of the first Cascade systems delivered by Cray. Is there any risk associated with this? Why did NERSC take this route?

Nick Wright: Over the years NERSC has taken calculated risks on numerous occasions by deploying a low serial number version of a system. This goes as far back as 1978, when a Cray-1 with serial number 6 was deployed, and 1985, when NERSC installed the first Cray-2 machine. Other examples include the T3E-900 installed in 1997, which was the largest I/O system built to date, and Hopper, one of the first Cray XE6 machines, deployed in 2009. There are significant benefits for the NERSC user community in terms of increased scientific output from having access to the latest, highest-performing technology. Also, there are significant benefits to NERSC and its sponsors because utilizing the latest technology maximizes the useful lifetime of a system and the return on investment. In this case, the Cray Cascade system has both the latest Intel processors and the highly scalable Aries interconnect, both of which are already delivering exceptional performance to our users.

JB: Additionally, Edison has a novel cooling scheme that will allow us to move it to the Computational Research and Theory (CRT) Center, our new facility now under construction. CRT will use “free” cooling using only outside air and cooling towers. Thanks to our Bay Area climate, we can run this way year round without the added cost of mechanical chillers. Cascade is designed to operate with the warmer air and water temperatures that we can expect during certain parts of the year.

Edison has proven to be very reliable right out of the starting gate. Phase 1 of the system was installed in late 2012, and has already proven very popular with our users.

Bashor: Not only is this the first Cray machine to use Intel processors, but it also incorporates the new Aries interconnect and the Cray Sonexion storage system. What will this mean for NERSC’s 4,500 users?

Sudip Dosanjh: We believe Edison will be a very productive system for our users. It has very high memory bandwidth, memory capacity and interconnect bandwidth relative to its compute capability. Data movement is the limiting factor for a large fraction of the 600 codes that run at NERSC. Floating point units are often idle waiting for data to arrive. Many codes spend a few percent of their total runtime performing floating point operations, the rest of the time is spent accessing memory or calculating memory addresses. Edison will be a very effective platform for running the very broad range of science codes at NERSC.

JB: In short, Edison will be a very scalable and robust system for the broad range of users that NERSC has. We support more than 700 projects across all the program offices of the Department of Energy’s Office of Science: Advanced Scientific Computing Research, Basic Energy Sciences, Biological and Environmental Research, Fusion Energy Sciences, High Energy Physics and Nuclear Physics. The Intel processors and Aries interconnect have delivered good performance on a diverse class of algorithms.

Since the programming and operating environment is essentially the same as Hopper, it’s been extremely easy for users to move codes from one system to another, even on a day-to-day basis. It just takes a simple recompile to optimize performance.

NW: NERSC users are frequently performing science runs at scale, both to generate science results as well as explore the capabilities and limitations of their codes. The capabilities of the new highly scalable Aries interconnect will enable greater performance at scale and will deliver significant sustained performance.

Bashor: The system also provides 64 GB of memory per node. How is this different from other systems and what’s the benefit to users?

NW: We could have purchased Edison configured with 32 GB per node and spent the money saved on boosting the peak flops of the system. As Jeff said though, our focus is on enabling scientific productivity and we felt the benefits to users from extra memory far out weighed those that a slightly higher peak flop rating would have delivered. The 64 GB per node is twice the amount of memory we have per node in Hopper. This will allow those codes that are more data-intensive to process more quickly and to solve larger problems.

Bashor: NERSC’s future home, the CRT center currently under construction in Berkeley, will use the Bay Area’s “natural air conditioning” to cool the machine room and improve efficiency. What’s being done in the meantime?

JB: At our current facility in Oakland, we have essentially the same climate, and we are prototyping the CRT cooling infrastructure using Edison. We removed 1,100 tons of chillers and replaced them with heat exchangers. Cooling comes from evaporation in cooling towers exclusively. This gives us an opportunity to test the principles we are implementing and adjust the CRT design as needed. The expected PUE (power usage effectiveness) for Edison is approximately 1.1, which represents a two-thirds savings in the energy costs for cooling compared to similar systems cooled with mechanical chillers.

Next >> Looking Farther Ahead

Bashor: Looking farther ahead to exascale, NERSC’s 4,500 users and their 600 applications will face some real challenges to maintain their current scientific productivity of 1,500 papers each year. How will you manage the transition to exascale systems from the users’ perspective?

SD: Exascale computing will impact all scales of computing from supercomputers to racks because the fundamental building blocks, processors and memory, are changing dramatically. Clock speeds are expected to remain near a GigaHertz for the foreseeable future, and the concurrency in processors is expected to increase at a Moore’s Law pace. All of the codes running at NERSC will need to transition to energy efficient architectures during the next few years. If we can’t make this leap, users will be stuck at today’s performance levels and we will miss many opportunities for scientific discovery. We will work with our users to make this transition as smooth as possible. We have started an application readiness effort to begin transitioning our codes in the NERSC-8 time frame.

JB: As I mentioned, our plan is to start transitioning users to exascale programming models – which will involve increased parallelism and non-transparent memory hierarchies – with our procurement of the NERSC-8 system, which will arrive in late 2015. We expect this system to be some variety of a GPU or manycore architecture.

Of the 600 applications running on NERSC systems, we know that just 10 of them account for about 50 percent of the time used on the machines. We will make a concerted effort to port those codes to NERSC-8. There will still be a number of applications that will be difficult or not cost-effective to immediately transition to the new machine, so they will stay on Edison and be given more time to transition. We see Edison as a kind of safety net for users of those applications.

Bashor: Last question. NERSC recently completed its 10-year strategic plan. Can you give us a short summary of where the center expects to be in 10 years?

SD: The aggregate computing needs of Office of Science research teams at NERSC will be well into the exascale regime by the end of the decade. Science teams need to run simulations at hundreds of petaflop/s, and they need to run thousands to millions of petascale simulations. We will deploy pre-exascale systems in 2016 and 2019. We anticipate deploying our first exascale system, NERSC-10, in 2022.

We are also seeing the growing importance of big data and many recent scientific breakthroughs enabled by NERSC involve large data sets. For the past four years, our users have imported more data to NERSC to analyze than they have exported. Many months, we import more than a petabyte of data! We will begin enhancing our data capabilities starting in 2014, and we will deploy data systems, storage, advanced networking, and enhanced user services so that current users and DOE experimental facilities can move and process exabytes of data early in the next decade.

While we have talked a lot about systems in this interview, I want to close by talking about the most critical component of NERSC’s very successful 39-year history – our staff. We run a very effective operation, operating Edison, Hopper, three large clusters, a 20-petabyte HPSS data archive and more, all stitched together seamlessly by the NERSC Global Filesystem. On the services side, we providing extensive technical support to our 4,500 users as well as providing the intellectual infrastructure needed to advance scientific discovery across DOE’s research mission areas. Our users are also very complimentary of our staff – consistently giving us excellent scores in our annual survey. Achieving this requires both extensive expertise and true dedication on the part of our staff. Although I only joined NERSC last fall, I am very proud to be part of such an accomplished organization.

About NERSC and Berkeley Lab

The National Energy Research Scientific Computing Center (NERSC) is the primary high-performance computing facility for scientific research sponsored by the U.S. Department of Energy’s Office of Science. Located at Lawrence Berkeley National Laboratory, the NERSC Center serves more than 4,000 scientists at national laboratories and universities researching a wide range of problems in combustion, climate modeling, fusion energy, materials science, physics, chemistry, computational biology, and other disciplines. Berkeley Lab is a U.S. Department of Energy national laboratory located in Berkeley, California. It conducts unclassified scientific research and is managed by the University of California for the U.S. DOE Office of Science. For more information about computing sciences at Berkeley Lab, please visit www.lbl.gov/cs.

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

Enlisting Deep Learning in the War on Cancer

December 7, 2016

Sometime in Q2 2017 the first ‘results’ of the Joint Design of Advanced Computing Solutions for Cancer (JDACS4C) will become publicly available according to Rick Stevens. He leads one of three JDACS4C pilot projects pressing deep learning (DL) into service in the War on Cancer. The pilots, supported in part by DOE exascale funding, not only seek to do good by advancing cancer research and therapy but also to advance deep learning capabilities and infrastructure with an eye towards eventual use on exascale machines. Read more…

By John Russell

DDN Enables 50TB/Day Trans-Pacific Data Transfer for Yahoo Japan

December 6, 2016

Transferring data from one data center to another in search of lower regional energy costs isn’t a new concept, but Yahoo Japan is putting the idea into transcontinental effect with a system that transfers 50TB of data a day from Japan to the U.S., where electricity costs a quarter of the rates in Japan. Read more…

By Doug Black

Infographic Highlights Career of Admiral Grace Murray Hopper

December 5, 2016

Dr. Grace Murray Hopper (December 9, 1906 – January 1, 1992) was an early pioneer of computer science and one of the most famous women achievers in a field dominated by men. Read more…

By Staff

Ganthier, Turkel on the Dell EMC Road Ahead

December 5, 2016

Who is Dell EMC and why should you care? Glad you asked is Jim Ganthier’s quick response. Ganthier is SVP for validated solutions and high performance computing for the new (even bigger) technology giant Dell EMC following Dell’s acquisition of EMC in September. In this case, says Ganthier, the blending of the two companies is a 1+1 = 5 proposition. Not bad math if you can pull it off. Read more…

By John Russell

AWS Embraces FPGAs, ‘Elastic’ GPUs

December 2, 2016

A new instance type rolled out this week by Amazon Web Services is based on customizable field programmable gate arrays that promise to strike a balance between performance and cost as emerging workloads create requirements often unmet by general-purpose processors. Read more…

By George Leopold

AWS Launches Massive 100 Petabyte ‘Sneakernet’

December 1, 2016

Amazon Web Services now offers a way to move data into its cloud by the truckload. Read more…

By Tiffany Trader

Weekly Twitter Roundup (Dec. 1, 2016)

December 1, 2016

Here at HPCwire, we aim to keep the HPC community apprised of the most relevant and interesting news items that get tweeted throughout the week. Read more…

By Thomas Ayres

HPC Career Notes (Dec. 2016)

December 1, 2016

In this monthly feature, we’ll keep you up-to-date on the latest career developments for individuals in the high performance computing community. Read more…

By Thomas Ayres

Enlisting Deep Learning in the War on Cancer

December 7, 2016

Sometime in Q2 2017 the first ‘results’ of the Joint Design of Advanced Computing Solutions for Cancer (JDACS4C) will become publicly available according to Rick Stevens. He leads one of three JDACS4C pilot projects pressing deep learning (DL) into service in the War on Cancer. The pilots, supported in part by DOE exascale funding, not only seek to do good by advancing cancer research and therapy but also to advance deep learning capabilities and infrastructure with an eye towards eventual use on exascale machines. Read more…

By John Russell

Ganthier, Turkel on the Dell EMC Road Ahead

December 5, 2016

Who is Dell EMC and why should you care? Glad you asked is Jim Ganthier’s quick response. Ganthier is SVP for validated solutions and high performance computing for the new (even bigger) technology giant Dell EMC following Dell’s acquisition of EMC in September. In this case, says Ganthier, the blending of the two companies is a 1+1 = 5 proposition. Not bad math if you can pull it off. Read more…

By John Russell

AWS Launches Massive 100 Petabyte ‘Sneakernet’

December 1, 2016

Amazon Web Services now offers a way to move data into its cloud by the truckload. Read more…

By Tiffany Trader

Lighting up Aurora: Behind the Scenes at the Creation of the DOE’s Upcoming 200 Petaflops Supercomputer

December 1, 2016

In April 2015, U.S. Department of Energy Undersecretary Franklin Orr announced that Intel would be the prime contractor for Aurora: Read more…

By Jan Rowell

Seagate-led SAGE Project Delivers Update on Exascale Goals

November 29, 2016

Roughly a year and a half after its launch, the SAGE exascale storage project led by Seagate has delivered a substantive interim report – Data Storage for Extreme Scale. Read more…

By John Russell

Nvidia Sees Bright Future for AI Supercomputing

November 23, 2016

Graphics chipmaker Nvidia made a strong showing at SC16 in Salt Lake City last week. Read more…

By Tiffany Trader

HPE-SGI to Tackle Exascale and Enterprise Targets

November 22, 2016

At first blush, and maybe second blush too, Hewlett Packard Enterprise’s (HPE) purchase of SGI seems like an unambiguous win-win. SGI’s advanced shared memory technology, its popular UV product line (Hanna), deep vertical market expertise, and services-led go-to-market capability all give HPE a leg up in its drive to remake itself. Bear in mind HPE came into existence just a year ago with the split of Hewlett-Packard. The computer landscape, including HPC, is shifting with still unclear consequences. One wonders who’s next on the deal block following Dell’s recent merger with EMC. Read more…

By John Russell

Intel Details AI Hardware Strategy for Post-GPU Age

November 21, 2016

Last week at SC16, Intel revealed its product roadmap for embedding its processors with key capabilities and attributes needed to take artificial intelligence (AI) to the next level. Read more…

By Alex Woodie

Why 2016 Is the Most Important Year in HPC in Over Two Decades

August 23, 2016

In 1994, two NASA employees connected 16 commodity workstations together using a standard Ethernet LAN and installed open-source message passing software that allowed their number-crunching scientific application to run on the whole “cluster” of machines as if it were a single entity. Read more…

By Vincent Natoli, Stone Ridge Technology

IBM Advances Against x86 with Power9

August 30, 2016

After offering OpenPower Summit attendees a limited preview in April, IBM is unveiling further details of its next-gen CPU, Power9, which the tech mainstay is counting on to regain market share ceded to rival Intel. Read more…

By Tiffany Trader

AWS Beats Azure to K80 General Availability

September 30, 2016

Amazon Web Services has seeded its cloud with Nvidia Tesla K80 GPUs to meet the growing demand for accelerated computing across an increasingly-diverse range of workloads. The P2 instance family is a welcome addition for compute- and data-focused users who were growing frustrated with the performance limitations of Amazon's G2 instances, which are backed by three-year-old Nvidia GRID K520 graphics cards. Read more…

By Tiffany Trader

Think Fast – Is Neuromorphic Computing Set to Leap Forward?

August 15, 2016

Steadily advancing neuromorphic computing technology has created high expectations for this fundamentally different approach to computing. Read more…

By John Russell

The Exascale Computing Project Awards $39.8M to 22 Projects

September 7, 2016

The Department of Energy’s Exascale Computing Project (ECP) hit an important milestone today with the announcement of its first round of funding, moving the nation closer to its goal of reaching capable exascale computing by 2023. Read more…

By Tiffany Trader

HPE Gobbles SGI for Larger Slice of $11B HPC Pie

August 11, 2016

Hewlett Packard Enterprise (HPE) announced today that it will acquire rival HPC server maker SGI for $7.75 per share, or about $275 million, inclusive of cash and debt. The deal ends the seven-year reprieve that kept the SGI banner flying after Rackable Systems purchased the bankrupt Silicon Graphics Inc. for $25 million in 2009 and assumed the SGI brand. Bringing SGI into its fold bolsters HPE's high-performance computing and data analytics capabilities and expands its position... Read more…

By Tiffany Trader

ARM Unveils Scalable Vector Extension for HPC at Hot Chips

August 22, 2016

ARM and Fujitsu today announced a scalable vector extension (SVE) to the ARMv8-A architecture intended to enhance ARM capabilities in HPC workloads. Fujitsu is the lead silicon partner in the effort (so far) and will use ARM with SVE technology in its post K computer, Japan’s next flagship supercomputer planned for the 2020 timeframe. This is an important incremental step for ARM, which seeks to push more aggressively into mainstream and HPC server markets. Read more…

By John Russell

IBM Debuts Power8 Chip with NVLink and Three New Systems

September 8, 2016

Not long after revealing more details about its next-gen Power9 chip due in 2017, IBM today rolled out three new Power8-based Linux servers and a new version of its Power8 chip featuring Nvidia’s NVLink interconnect. Read more…

By John Russell

Leading Solution Providers

Vectors: How the Old Became New Again in Supercomputing

September 26, 2016

Vector instructions, once a powerful performance innovation of supercomputing in the 1970s and 1980s became an obsolete technology in the 1990s. But like the mythical phoenix bird, vector instructions have arisen from the ashes. Here is the history of a technology that went from new to old then back to new. Read more…

By Lynd Stringer

US, China Vie for Supercomputing Supremacy

November 14, 2016

The 48th edition of the TOP500 list is fresh off the presses and while there is no new number one system, as previously teased by China, there are a number of notable entrants from the US and around the world and significant trends to report on. Read more…

By Tiffany Trader

Intel Launches Silicon Photonics Chip, Previews Next-Gen Phi for AI

August 18, 2016

At the Intel Developer Forum, held in San Francisco this week, Intel Senior Vice President and General Manager Diane Bryant announced the launch of Intel's Silicon Photonics product line and teased a brand-new Phi product, codenamed "Knights Mill," aimed at machine learning workloads. Read more…

By Tiffany Trader

CPU Benchmarking: Haswell Versus POWER8

June 2, 2015

With OpenPOWER activity ramping up and IBM’s prominent role in the upcoming DOE machines Summit and Sierra, it’s a good time to look at how the IBM POWER CPU stacks up against the x86 Xeon Haswell CPU from Intel. Read more…

By Tiffany Trader

Beyond von Neumann, Neuromorphic Computing Steadily Advances

March 21, 2016

Neuromorphic computing – brain inspired computing – has long been a tantalizing goal. The human brain does with around 20 watts what supercomputers do with megawatts. And power consumption isn’t the only difference. Fundamentally, brains ‘think differently’ than the von Neumann architecture-based computers. While neuromorphic computing progress has been intriguing, it has still not proven very practical. Read more…

By John Russell

Dell EMC Engineers Strategy to Democratize HPC

September 29, 2016

The freshly minted Dell EMC division of Dell Technologies is on a mission to take HPC mainstream with a strategy that hinges on engineered solutions, beginning with a focus on three industry verticals: manufacturing, research and life sciences. "Unlike traditional HPC where everybody bought parts, assembled parts and ran the workloads and did iterative engineering, we want folks to focus on time to innovation and let us worry about the infrastructure," said Jim Ganthier, senior vice president, validated solutions organization at Dell EMC Converged Platforms Solution Division. Read more…

By Tiffany Trader

Container App ‘Singularity’ Eases Scientific Computing

October 20, 2016

HPC container platform Singularity is just six months out from its 1.0 release but already is making inroads across the HPC research landscape. It's in use at Lawrence Berkeley National Laboratory (LBNL), where Singularity founder Gregory Kurtzer has worked in the High Performance Computing Services (HPCS) group for 16 years. Read more…

By Tiffany Trader

Micron, Intel Prepare to Launch 3D XPoint Memory

August 16, 2016

Micron Technology used last week’s Flash Memory Summit to roll out its new line of 3D XPoint memory technology jointly developed with Intel while demonstrating the technology in solid-state drives. Micron claimed its Quantx line delivers PCI Express (PCIe) SSD performance with read latencies at less than 10 microseconds and writes at less than 20 microseconds. Read more…

By George Leopold

  • arrow
  • Click Here for More Headlines
  • arrow
Share This