NERSC Managers Shed Light on ‘Edison’

By Nicole Hemsoth

April 29, 2013

At the end of March, the Department of Energy’s National Energy Research Scientific Computing (NERSC) Center accepted the first phase of its new Cray Cascade system. Named Edison, the new machine is a Cray XC30 with 664 compute nodes and 10,624 cores. Each node has two eight-core Intel “Sandy Bridge” processors running at 2.6 GHz (16 cores per node), and has 64 GB of memory.

While the user environment on Edison is remarkably similar to that on Hopper, NERSC’s current main system, a number of new features and technologies are available on the Edison Phase I system, including the Cray Aries high speed interconnect, Hyper-Threading technology, the Sonexion storage system, and an external batch server. Once fully installed later in 2013, Edison will have a peak performance of more than 2 petaflop/s. The integrated storage system will have more than 6 petabytes (PB) of storage with an I/O bandwidth of 140 gigabytes (GB) per second.

Bucking the trend toward GPUs and hybrid architectures, Edison will use Intel processors exclusively. To find out the reasoning behind the design and deployment of Edison and what it means to NERSC’s 4,500 users, Jon Bashor of Berkeley Lab Computing Sciences spoke with NERSC Division Director Sudip Dosanjh, NERSC Systems Department Head Jeff Broughton and Advanced Technologies Group Leader Nick Wright.


Jon Bashor: First of all, how did the system come to be named Edison?

Jeff Broughton: At NERSC, we name our computers after famous scientists, like Hopper for Grace Hopper and Franklin for Benjamin Franklin. In this case, we were looking for someone iconic, someone who represented American team science. Thomas Edison was the obvious choice, especially for his work in the field of energy. His work had practical applications, and while NERSC supports mainly basic research, naming the system after Edison will be a constant reminder to consider the applied connotations of the science we support.

Bashor: When the procurement was announced in June 2012, the new system was described as delivering more than 2 petaflop/s peak performance, about twice that of Hopper. When other centers announce procurements, the new systems often provide an order of magnitude increase in performance. Is NERSC exiting the peak performance race?

JB: Although NERSC systems in the past have been highly ranked, NERSC has never been part of the peak performance “race.” We have always focused on the sustained performance of scientific applications as the basis for our procurements. For the most part, over the past 10 years, sustained performance has been a relatively constant fraction of peak performance. But with the move to GPUs and manycore systems, it has become increasingly difficult to maintain the traditional sustained/peak ratio. Getting users to move to these new architectures requires a major effort to port their applications.

As we transition to the path to exascale over the next decade, we think we can ask our 4,500 users to make the move to an entirely new class of architecture only once. We made a conscious decision that this is not the time for our users to make the transition and to let the architectures get sorted out before making that move. Our next system, now referred to as NERSC-8, will adopt one of the new energy-efficient architectures.

We are also seeing in our user community a big increase in data-intensive computing, with a focus on high throughput and single-node performance, so another goal was to provide a system that could meet the needs of data-intensive applications while continuing to support conventional HPC.

And we will continue to apply one of our unofficial benchmarks – the number of published research articles published by our users based on calculations performed at NERSC. We’ve averaged 1,500 per year for the past five years – another example of the sustained performance we are most interested in.

Bashor: Edison will be one of the first Cascade systems delivered by Cray. Is there any risk associated with this? Why did NERSC take this route?

Nick Wright: Over the years NERSC has taken calculated risks on numerous occasions by deploying a low serial number version of a system. This goes as far back as 1978, when a Cray-1 with serial number 6 was deployed, and 1985, when NERSC installed the first Cray-2 machine. Other examples include the T3E-900 installed in 1997, which was the largest I/O system built to date, and Hopper, one of the first Cray XE6 machines, deployed in 2009. There are significant benefits for the NERSC user community in terms of increased scientific output from having access to the latest, highest-performing technology. Also, there are significant benefits to NERSC and its sponsors because utilizing the latest technology maximizes the useful lifetime of a system and the return on investment. In this case, the Cray Cascade system has both the latest Intel processors and the highly scalable Aries interconnect, both of which are already delivering exceptional performance to our users.

JB: Additionally, Edison has a novel cooling scheme that will allow us to move it to the Computational Research and Theory (CRT) Center, our new facility now under construction. CRT will use “free” cooling using only outside air and cooling towers. Thanks to our Bay Area climate, we can run this way year round without the added cost of mechanical chillers. Cascade is designed to operate with the warmer air and water temperatures that we can expect during certain parts of the year.

Edison has proven to be very reliable right out of the starting gate. Phase 1 of the system was installed in late 2012, and has already proven very popular with our users.

Bashor: Not only is this the first Cray machine to use Intel processors, but it also incorporates the new Aries interconnect and the Cray Sonexion storage system. What will this mean for NERSC’s 4,500 users?

Sudip Dosanjh: We believe Edison will be a very productive system for our users. It has very high memory bandwidth, memory capacity and interconnect bandwidth relative to its compute capability. Data movement is the limiting factor for a large fraction of the 600 codes that run at NERSC. Floating point units are often idle waiting for data to arrive. Many codes spend a few percent of their total runtime performing floating point operations, the rest of the time is spent accessing memory or calculating memory addresses. Edison will be a very effective platform for running the very broad range of science codes at NERSC.

JB: In short, Edison will be a very scalable and robust system for the broad range of users that NERSC has. We support more than 700 projects across all the program offices of the Department of Energy’s Office of Science: Advanced Scientific Computing Research, Basic Energy Sciences, Biological and Environmental Research, Fusion Energy Sciences, High Energy Physics and Nuclear Physics. The Intel processors and Aries interconnect have delivered good performance on a diverse class of algorithms.

Since the programming and operating environment is essentially the same as Hopper, it’s been extremely easy for users to move codes from one system to another, even on a day-to-day basis. It just takes a simple recompile to optimize performance.

NW: NERSC users are frequently performing science runs at scale, both to generate science results as well as explore the capabilities and limitations of their codes. The capabilities of the new highly scalable Aries interconnect will enable greater performance at scale and will deliver significant sustained performance.

Bashor: The system also provides 64 GB of memory per node. How is this different from other systems and what’s the benefit to users?

NW: We could have purchased Edison configured with 32 GB per node and spent the money saved on boosting the peak flops of the system. As Jeff said though, our focus is on enabling scientific productivity and we felt the benefits to users from extra memory far out weighed those that a slightly higher peak flop rating would have delivered. The 64 GB per node is twice the amount of memory we have per node in Hopper. This will allow those codes that are more data-intensive to process more quickly and to solve larger problems.

Bashor: NERSC’s future home, the CRT center currently under construction in Berkeley, will use the Bay Area’s “natural air conditioning” to cool the machine room and improve efficiency. What’s being done in the meantime?

JB: At our current facility in Oakland, we have essentially the same climate, and we are prototyping the CRT cooling infrastructure using Edison. We removed 1,100 tons of chillers and replaced them with heat exchangers. Cooling comes from evaporation in cooling towers exclusively. This gives us an opportunity to test the principles we are implementing and adjust the CRT design as needed. The expected PUE (power usage effectiveness) for Edison is approximately 1.1, which represents a two-thirds savings in the energy costs for cooling compared to similar systems cooled with mechanical chillers.

Next >> Looking Farther Ahead

Bashor: Looking farther ahead to exascale, NERSC’s 4,500 users and their 600 applications will face some real challenges to maintain their current scientific productivity of 1,500 papers each year. How will you manage the transition to exascale systems from the users’ perspective?

SD: Exascale computing will impact all scales of computing from supercomputers to racks because the fundamental building blocks, processors and memory, are changing dramatically. Clock speeds are expected to remain near a GigaHertz for the foreseeable future, and the concurrency in processors is expected to increase at a Moore’s Law pace. All of the codes running at NERSC will need to transition to energy efficient architectures during the next few years. If we can’t make this leap, users will be stuck at today’s performance levels and we will miss many opportunities for scientific discovery. We will work with our users to make this transition as smooth as possible. We have started an application readiness effort to begin transitioning our codes in the NERSC-8 time frame.

JB: As I mentioned, our plan is to start transitioning users to exascale programming models – which will involve increased parallelism and non-transparent memory hierarchies – with our procurement of the NERSC-8 system, which will arrive in late 2015. We expect this system to be some variety of a GPU or manycore architecture.

Of the 600 applications running on NERSC systems, we know that just 10 of them account for about 50 percent of the time used on the machines. We will make a concerted effort to port those codes to NERSC-8. There will still be a number of applications that will be difficult or not cost-effective to immediately transition to the new machine, so they will stay on Edison and be given more time to transition. We see Edison as a kind of safety net for users of those applications.

Bashor: Last question. NERSC recently completed its 10-year strategic plan. Can you give us a short summary of where the center expects to be in 10 years?

SD: The aggregate computing needs of Office of Science research teams at NERSC will be well into the exascale regime by the end of the decade. Science teams need to run simulations at hundreds of petaflop/s, and they need to run thousands to millions of petascale simulations. We will deploy pre-exascale systems in 2016 and 2019. We anticipate deploying our first exascale system, NERSC-10, in 2022.

We are also seeing the growing importance of big data and many recent scientific breakthroughs enabled by NERSC involve large data sets. For the past four years, our users have imported more data to NERSC to analyze than they have exported. Many months, we import more than a petabyte of data! We will begin enhancing our data capabilities starting in 2014, and we will deploy data systems, storage, advanced networking, and enhanced user services so that current users and DOE experimental facilities can move and process exabytes of data early in the next decade.

While we have talked a lot about systems in this interview, I want to close by talking about the most critical component of NERSC’s very successful 39-year history – our staff. We run a very effective operation, operating Edison, Hopper, three large clusters, a 20-petabyte HPSS data archive and more, all stitched together seamlessly by the NERSC Global Filesystem. On the services side, we providing extensive technical support to our 4,500 users as well as providing the intellectual infrastructure needed to advance scientific discovery across DOE’s research mission areas. Our users are also very complimentary of our staff – consistently giving us excellent scores in our annual survey. Achieving this requires both extensive expertise and true dedication on the part of our staff. Although I only joined NERSC last fall, I am very proud to be part of such an accomplished organization.

About NERSC and Berkeley Lab

The National Energy Research Scientific Computing Center (NERSC) is the primary high-performance computing facility for scientific research sponsored by the U.S. Department of Energy’s Office of Science. Located at Lawrence Berkeley National Laboratory, the NERSC Center serves more than 4,000 scientists at national laboratories and universities researching a wide range of problems in combustion, climate modeling, fusion energy, materials science, physics, chemistry, computational biology, and other disciplines. Berkeley Lab is a U.S. Department of Energy national laboratory located in Berkeley, California. It conducts unclassified scientific research and is managed by the University of California for the U.S. DOE Office of Science. For more information about computing sciences at Berkeley Lab, please visit www.lbl.gov/cs.

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

IBM Launches Commercial Quantum Network with Samsung, ORNL

December 14, 2017

In the race to commercialize quantum computing, IBM is one of several companies leading the pack. Today, IBM announced it had signed JPMorgan Chase, Daimler AG, Samsung and a number of other corporations to its IBM Q Net Read more…

By Tiffany Trader

TACC Researchers Test AI Traffic Monitoring Tool in Austin

December 13, 2017

Traffic jams and mishaps are often painful and sometimes dangerous facts of life. At this week’s IEEE International Conference on Big Data being held in Boston, researchers from TACC and colleagues will present a new Read more…

By HPCwire Staff

AMD Wins Another: Baidu to Deploy EPYC on Single Socket Servers

December 13, 2017

When AMD introduced its EPYC chip line in June, the company said a portion of the line was specifically designed to re-invigorate a single socket segment in what has become an overwhelmingly two-socket landscape in the d Read more…

By John Russell

HPE Extreme Performance Solutions

Explore the Origins of Space with COSMOS and Memory-Driven Computing

From the formation of black holes to the origins of space, data is the key to unlocking the secrets of the early universe. Read more…

Microsoft Wants to Speed Quantum Development

December 12, 2017

Quantum computing continues to make headlines in what remains of 2017 as several tech giants jockey to establish a pole position in the race toward commercialization of quantum. This week, Microsoft took the next step in Read more…

By Tiffany Trader

IBM Launches Commercial Quantum Network with Samsung, ORNL

December 14, 2017

In the race to commercialize quantum computing, IBM is one of several companies leading the pack. Today, IBM announced it had signed JPMorgan Chase, Daimler AG, Read more…

By Tiffany Trader

AMD Wins Another: Baidu to Deploy EPYC on Single Socket Servers

December 13, 2017

When AMD introduced its EPYC chip line in June, the company said a portion of the line was specifically designed to re-invigorate a single socket segment in wha Read more…

By John Russell

Microsoft Wants to Speed Quantum Development

December 12, 2017

Quantum computing continues to make headlines in what remains of 2017 as several tech giants jockey to establish a pole position in the race toward commercializ Read more…

By Tiffany Trader

HPC Iron, Soft, Data, People – It Takes an Ecosystem!

December 11, 2017

Cutting edge advanced computing hardware (aka big iron) does not stand by itself. These computers are the pinnacle of a myriad of technologies that must be care Read more…

By Alex R. Larzelere

IBM Begins Power9 Rollout with Backing from DOE, Google

December 6, 2017

After over a year of buildup, IBM is unveiling its first Power9 system based on the same architecture as the Department of Energy CORAL supercomputers, Summit a Read more…

By Tiffany Trader

Microsoft Spins Cycle Computing into Core Azure Product

December 5, 2017

Last August, cloud giant Microsoft acquired HPC cloud orchestration pioneer Cycle Computing. Since then the focus has been on integrating Cycle’s organization Read more…

By John Russell

GlobalFoundries, Ayar Labs Team Up to Commercialize Optical I/O

December 4, 2017

GlobalFoundries (GF) and Ayar Labs, a startup focused on using light, instead of electricity, to transfer data between chips, today announced they've entered in Read more…

By Tiffany Trader

HPE In-Memory Platform Comes to COSMOS

November 30, 2017

Hewlett Packard Enterprise is on a mission to accelerate space research. In August, it sent the first commercial-off-the-shelf HPC system into space for testing Read more…

By Tiffany Trader

US Coalesces Plans for First Exascale Supercomputer: Aurora in 2021

September 27, 2017

At the Advanced Scientific Computing Advisory Committee (ASCAC) meeting, in Arlington, Va., yesterday (Sept. 26), it was revealed that the "Aurora" supercompute Read more…

By Tiffany Trader

NERSC Scales Scientific Deep Learning to 15 Petaflops

August 28, 2017

A collaborative effort between Intel, NERSC and Stanford has delivered the first 15-petaflops deep learning software running on HPC platforms and is, according Read more…

By Rob Farber

Oracle Layoffs Reportedly Hit SPARC and Solaris Hard

September 7, 2017

Oracle’s latest layoffs have many wondering if this is the end of the line for the SPARC processor and Solaris OS development. As reported by multiple sources Read more…

By John Russell

AMD Showcases Growing Portfolio of EPYC and Radeon-based Systems at SC17

November 13, 2017

AMD’s charge back into HPC and the datacenter is on full display at SC17. Having launched the EPYC processor line in June along with its MI25 GPU the focus he Read more…

By John Russell

Nvidia Responds to Google TPU Benchmarking

April 10, 2017

Nvidia highlights strengths of its newest GPU silicon in response to Google's report on the performance and energy advantages of its custom tensor processor. Read more…

By Tiffany Trader

Japan Unveils Quantum Neural Network

November 22, 2017

The U.S. and China are leading the race toward productive quantum computing, but it's early enough that ultimate leadership is still something of an open questi Read more…

By Tiffany Trader

GlobalFoundries Puts Wind in AMD’s Sails with 12nm FinFET

September 24, 2017

From its annual tech conference last week (Sept. 20), where GlobalFoundries welcomed more than 600 semiconductor professionals (reaching the Santa Clara venue Read more…

By Tiffany Trader

Amazon Debuts New AMD-based GPU Instances for Graphics Acceleration

September 12, 2017

Last week Amazon Web Services (AWS) streaming service, AppStream 2.0, introduced a new GPU instance called Graphics Design intended to accelerate graphics. The Read more…

By John Russell

Leading Solution Providers

IBM Begins Power9 Rollout with Backing from DOE, Google

December 6, 2017

After over a year of buildup, IBM is unveiling its first Power9 system based on the same architecture as the Department of Energy CORAL supercomputers, Summit a Read more…

By Tiffany Trader

Perspective: What Really Happened at SC17?

November 22, 2017

SC is over. Now comes the myriad of follow-ups. Inboxes are filled with templated emails from vendors and other exhibitors hoping to win a place in the post-SC thinking of booth visitors. Attendees of tutorials, workshops and other technical sessions will be inundated with requests for feedback. Read more…

By Andrew Jones

EU Funds 20 Million Euro ARM+FPGA Exascale Project

September 7, 2017

At the Barcelona Supercomputer Centre on Wednesday (Sept. 6), 16 partners gathered to launch the EuroEXA project, which invests €20 million over three-and-a-half years into exascale-focused research and development. Led by the Horizon 2020 program, EuroEXA picks up the banner of a triad of partner projects — ExaNeSt, EcoScale and ExaNoDe — building on their work... Read more…

By Tiffany Trader

Delays, Smoke, Records & Markets – A Candid Conversation with Cray CEO Peter Ungaro

October 5, 2017

Earlier this month, Tom Tabor, publisher of HPCwire and I had a very personal conversation with Cray CEO Peter Ungaro. Cray has been on something of a Cinderell Read more…

By Tiffany Trader & Tom Tabor

Tensors Come of Age: Why the AI Revolution Will Help HPC

November 13, 2017

Thirty years ago, parallel computing was coming of age. A bitter battle began between stalwart vector computing supporters and advocates of various approaches to parallel computing. IBM skeptic Alan Karp, reacting to announcements of nCUBE’s 1024-microprocessor system and Thinking Machines’ 65,536-element array, made a public $100 wager that no one could get a parallel speedup of over 200 on real HPC workloads. Read more…

By John Gustafson & Lenore Mullin

Flipping the Flops and Reading the Top500 Tea Leaves

November 13, 2017

The 50th edition of the Top500 list, the biannual publication of the world’s fastest supercomputers based on public Linpack benchmarking results, was released Read more…

By Tiffany Trader

Intel Launches Software Tools to Ease FPGA Programming

September 5, 2017

Field Programmable Gate Arrays (FPGAs) have a reputation for being difficult to program, requiring expertise in specialty languages, like Verilog or VHDL. Easin Read more…

By Tiffany Trader

HPC Chips – A Veritable Smorgasbord?

October 10, 2017

For the first time since AMD's ill-fated launch of Bulldozer the answer to the question, 'Which CPU will be in my next HPC system?' doesn't have to be 'Whichever variety of Intel Xeon E5 they are selling when we procure'. Read more…

By Dairsie Latimer

  • arrow
  • Click Here for More Headlines
  • arrow
Share This