OpenCL: Free Your GPU… and the rest of your system too!

By Nicole Hemsoth

May 6, 2013

For the uninitiated, OpenCL may just seem like a tool for accessing GPUs in a portable manner, an alternative to CUDA that works for ATI cards.  This view of OpenCL is a vast oversimplification.  The truth is that OpenCL offers a rich set of features that will provide the infrastructure needed for application developers to fully utilize an increasingly heterogeneous hardware future.  In this article, we will consider how OpenCL can address some of the coming challenges, and what the OpenCL community is doing to insure that there is a vibrant ecosystem of support, as more and more users turn to OpenCL from vendor-locked solutions.

By now, we’ve all heard of the power wall, and we know that the only way to climb over it is parallelism.  Data-level parallelism (think GPUs) was the first technology to make a mark in the new computing age.  Employing very uniform work units, data-parallel implementations have achieved noteworthy performance gains for many scientific algorithms, and OpenCL certainly has support for this model.

However, this is not the end of the story.  As CPU vendors seek to adapt their architectures to the new parallel reality (and GPU vendors evolve theirs), alternate ideas about how to expose and exploit parallelism within a program are surfacing.  These designs seek to mitigate performance limitations for algorithms where the majority of the work does not fit neatly into non-divergent units of execution.

One such approach is to take a multicore architecture and scale it, providing increased resources for task-parallel workloads.  An example of this is the Intel Xeon Phi architecture, released in 2012.  Sharing similarities with CPUs and GPUs, the Xeon Phi programming model requires a little bit of both.  Like a CPU, the Xeon Phi prefers somewhat longer persistence from a work item, so that its caching scheme can work efficiently to hide memory access latency.  At the same time, the Xeon Phi offers many more units of execution than traditional SMP implementations are designed to handle.  For many applications, there is likely a good balance to be found that combines both data and task-parallelism, and fortunately for developers, Intel has provided OpenCL support for their entire processor line, including Xeon Phi and embedded graphics.  As an example of why this is beneficial, OpenCL has no problem expressing local accumulations, with or without blocked memory access, and its interface for managing work groups is sufficient for any level of data-parallel execution.  These features make it possible to seamlessly integrate mixed programming models that reflect the hybrid characteristics of the Xeon Phi hardware.

A third hardware strategy that has already been widely deployed, but not yet fully utilized (and often not even recognized) is the heterogeneous system-on-a-chip (SoC).  Founded with the now-extinct IBM Cell, and combining so-called latency-optimized cores (think CPU) with throughput-optimized cores (GPU), heterogeneous architectures attempt to provide the best of both worlds, albeit on separate parts of the die.  If you are reading this article on a mobile computing device, or a late model laptop or desktop, chances are that you already have a heterogeneous chip at your disposal: Apple A Series, NVIDIA Tegra, AMD Fusion, Qualcomm Snapdragon, and Intel Ivybridge are all heterogeneous.  Some of these chips are even likely to find their way onto the next generation of supercomputers.  If this is the case, and unless you are explicitly utilizing these resources, they can be an energy drain on your system with no benefit.  OpenCL makes the full potential of heterogeneous architectures available to the developer.

A final evolving hardware strategy that should be mentioned is the Field Programmable Gate Array (FPGA).  Few general-purpose processing architectures can compete with the energy efficiency of a custom circuit.  Sadly, very few developers are prepared to invest the time and effort needed to learn VHDL or Verilog to turn their ideas into a working core.  One very novel application of OpenCL seeks to remove this barrier by creating FPGA firmware from kernels written in the OpenCL C programming language.  The Altera Corporation (maker of the Stratix V architecture) has released the Altera SDK for OpenCL.  Using this set of tools, developers can generate custom hardware, tailor-made for their specific application.  This frees the application developer from the tedium of a job better left to electrical engineers, and, at the same time, opens a fascinating world of possibilities.

All of the hardware trends we have discussed, taken together, present significant challenges for any vendor-specific toolchain.  Consider the programming model for a system with a heterogeneous host processor, augmented with a discrete accelerator (GPU or other).  Efficient utilization of these resources will require the ability to tightly integrate both data-parallel and task-parallel work, along with data motion between the various compute units.  Do we really want to rely on a clumsy vendor-specific patchwork of tools to meet this challenge?  Imagine now that you must also support a similarly provisioned system but built from a different set of architectures.  How many versions of your code would you have to write?  How many man-years might you need for such a task?

With OpenCL, implementing such a model is straightforward.  This is because OpenCL is a natural reflection of the competing hardware architectures on which it is designed to run.  OpenCL accommodates each of the above architectures, and, by design, has no trouble in accommodating all of them together.  Being an open standard, new vendors are able to join the OpenCL dialogue, insuring that OpenCL will be able to support future hardware developments, regardless of what direction they may take.  Additionally, with its support for custom devices, OpenCL offers the flexibility to incorporate system resources that do not fit the current notion of a compute device, opening opportunities for integration of DSPs or internally developed ASICs.

Much of the FUD (fear, uncertainty and doubt) directed at OpenCL has focused on the mantra that OpenCL may be portable but not portably performant.  This is an attempt to divert the discussion from the real issue.  Clearly, all hardware is not the same, and no single approach to expressing a parallel algorithm can be optimal across the wide variety of architectures that are currently available.  This is not the point of OpenCL.  The true power of OpenCL is that it provides the infrastructure that allows us to target different combinations of hardware within a single framework.  OpenCL frees us from the old scenario where developers must use an ad hoc combination of interfaces to support multiple architectures.  True, we may need to write a new version of our kernel to get the best performance on Architecture A, but isn’t this what we actually want?  With OpenCL, developers can easily switch between different kernel implementations, execution topologies and memory model interpretations.  This flexibility is at the core of the OpenCL philosophy.  So, to the OpenCL detractors: A toad may criticize the way that a bird flaps its wings, but only to distract us from the fact that the toad cannot fly.

One thing that has thus far been missing from OpenCL is a formal organization for its users.  To remedy this, some of the primary advocates of OpenCL have organized a new user group.  Since OpenCL is about computing portability, this new group is aptly named Comportability.  Established as a non-profit corporation, Comportability is an open forum for all things related to OpenCL.  Membership is free.  Individuals are invited to participate in discussions, upload software and take part in the annual workshop.  Institutions and vendors may join as voting members, and are invited to form regional chapters, which are encouraged to host future meetings and workshops.

The 1st International Workshop on OpenCL (IWOCL), the annual meeting of the Comportability user group will take place May 13-14, 2013 at the Technology Square Research Building (TSRB) at the Georgia Institute of Technology in Atlanta, Georgia.  Registration for this event is open and the program is on-line.

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