Intel Snaps New Grips to HPC Hook

By Nicole Hemsoth

June 17, 2013

Back in 1997, Intel’s ASCI Red system stole the show for the 9th iteration of the Top500 list with 7,264 Pentium Pros clocked at 200 MHz (and later outfitted with Pentium II OverDrives at 333 MHz) and peak Linpack performance of 1.068 teraflops.

It took the chipmaker another 32 Top 500 rounds to score the primo spot with an all-Intel system–and just like ASCI Red, the new top super Tianhe-2 toppled records, and carved a rut to pave over for next-generation systems. The ASCI Red maintained its position at the top for three years until the IBM ASCI White slithered by it, just as the Tianhe-2 will likely dominate the list for at least two years, barring any major surprises.

Despite the diminished supercomputer focus organizationally at the time with the closure of their Supercomputing Division just before the ASCI Red win, the company has made significant strides to reshape that landscape–efforts that culminated many years later in a system that shattered performance records with 48,000 Xeon Phi coprocessors, 32,000 Xeons, and Linpack performance hovering at the 33.8 mark.

While it’s only the second time the company has fully owned a top system, some argue that this is the beginning of a new trend–one that Intel is spearheading.

IDC claims that the server business for supercomputing will expand by 36 percent from $11 billion to $15 billion over the next 4 years. And as we noted earlier this morning, the Top 500 founders, analyst community and end user groups are seeing massive uptake in accelerator and coprocessor adoption–with strong emphasis on Xeon Phi.

As the Top 500 organizers noted today, 403 systems in the Top 500 are Intel-based. And as Intel reminded, “Of those systems making their first appearance on the list, Intel-powered installations account for 98 percent. The June edition of the list had recorded 11 systems based on the Intel Xeon Phi coprocessor, including the Petaflops class systems like Milky Way 2 (Tianhe-2) at 54.9 PFlops and Stampede at 8.5 PFlops of peak performance.”

On the heels of this, IDC stated today in its brief on HPC coprocessor growth some surprising figures on the proportion of sites employing co-processors or accelerators in their HPC systems. They claim the number jumped from 28.2% in the 2011 version of the study to 76.9% in 2013. They added that coprocessors and accelerators advanced from slightly more than 1% of all processor parts in 2011 to 3.4% in 2013, with Intel Xeon Phi co-processors and NVIDIA GPUs running neck and neck for leadership, and FPGAs in a respectable third-place position.

Neck and neck for a product that’s been available for a relatively short time–at least compared to GPU? This is indeed a development–one that IDC analyst Steve Conway said today was a shocker, even for his group that keeps firm tabs on this market. While a solid number of these are being implemented for exploration only at this point, Intel is poised to take its rivals to task in the years ahead, which will light a fire under NVIDIA, AMD and others to keep pace.

Instead of letting the Tianhe-2 news ride by itself today, Intel kicked out some developments around two aspects of its business for this growing market. In addition to some new families of Xeon Phi that have been bred for various roles, Intel formally announced some news about its second-gen Knights Landing that can do double duty as a coprocessor or CPU while tapping the 14 nm process and their most recent 3D TriGate transistors. This gives users some choice–allowing them to use it as a PCIe card-based coprocessor for offloading Xeon math, or to tap it as a host processor that’s planted in the motherboard socket, doing all the same things one might expect of a primary processor–but this time with a coprocessor kick.

Intel says that when used as the CPU, Knights Landing will chuck some of the data transfer roadblocks users have over PCIe using other accelerators. Further, to target HPC performance, they will significantly increase the memory bandwidth across the Knights Landing kingdom via integrated on-package memory.

Outside of these Knights Landing revelations, they also let fly on their new generation of Phis that offer some alternatives in terms of performance, price, power, form factors and memory with the ultra performance-tuned 7100 family, and the 3100 family, which sacrifices some performance and options in favor of a lower price. They also added a new member to the 5100 family that spawned last year with the new 5120D, which is focused on higher density environments and hooks the sockets to a mini-board to please the blade crowd.

At this point, it looks like they’ve managed to snare some traction at the highest end of the HPC segment via systems like Stampede and Tianhe-2. But with the additional Phi offerings focused on more middle of the road systems, Intel is making a bet that the “missing middle” of users at the lower end of the Top 500 and just off its cliff who have been holding out on adopting coprocessors or accelerators will now have further incentive given more options in terms of price and performance.

 

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

UCSD, AIST Forge Tighter Alliance with AI-Focused MOU

January 18, 2018

The rich history of collaboration between UC San Diego and AIST in Japan is getting richer. The organizations entered into a five-year memorandum of understanding on January 10. The MOU represents the continuation of a 1 Read more…

By Tiffany Trader

New Blueprint for Converging HPC, Big Data

January 18, 2018

After five annual workshops on Big Data and Extreme-Scale Computing (BDEC), a group of international HPC heavyweights including Jack Dongarra (University of Tennessee), Satoshi Matsuoka (Tokyo Institute of Technology), Read more…

By John Russell

Researchers Measure Impact of ‘Meltdown’ and ‘Spectre’ Patches on HPC Workloads

January 17, 2018

Computer scientists from the Center for Computational Research, State University of New York (SUNY), University at Buffalo have examined the effect of Meltdown and Spectre security updates on the performance of popular H Read more…

By Tiffany Trader

HPE Extreme Performance Solutions

HPE and NREL Take Steps to Create a Sustainable, Energy-Efficient Data Center with an H2 Fuel Cell

As enterprises attempt to manage rising volumes of data, unplanned data center outages are becoming more common and more expensive. As the cost of downtime rises, enterprises lose out on productivity and valuable competitive advantage without access to their critical data. Read more…

Fostering Lustre Advancement Through Development and Contributions

January 17, 2018

Six months after organizational changes at Intel's High Performance Data (HPDD) division, most in the Lustre community have shed any initial apprehension around the potential changes that could affect or disrupt Lustre Read more…

By Carlos Aoki Thomaz

UCSD, AIST Forge Tighter Alliance with AI-Focused MOU

January 18, 2018

The rich history of collaboration between UC San Diego and AIST in Japan is getting richer. The organizations entered into a five-year memorandum of understandi Read more…

By Tiffany Trader

New Blueprint for Converging HPC, Big Data

January 18, 2018

After five annual workshops on Big Data and Extreme-Scale Computing (BDEC), a group of international HPC heavyweights including Jack Dongarra (University of Te Read more…

By John Russell

Researchers Measure Impact of ‘Meltdown’ and ‘Spectre’ Patches on HPC Workloads

January 17, 2018

Computer scientists from the Center for Computational Research, State University of New York (SUNY), University at Buffalo have examined the effect of Meltdown Read more…

By Tiffany Trader

Fostering Lustre Advancement Through Development and Contributions

January 17, 2018

Six months after organizational changes at Intel's High Performance Data (HPDD) division, most in the Lustre community have shed any initial apprehension aroun Read more…

By Carlos Aoki Thomaz

When the Chips Are Down

January 11, 2018

In the last article, "The High Stakes Semiconductor Game that Drives HPC Diversity," I alluded to the challenges facing the semiconductor industry and how that may impact the evolution of HPC systems over the next few years. I thought I’d lift the covers a little and look at some of the commercial challenges that impact the component technology we use in HPC. Read more…

By Dairsie Latimer

How Meltdown and Spectre Patches Will Affect HPC Workloads

January 10, 2018

There have been claims that the fixes for the Meltdown and Spectre security vulnerabilities, named the KPTI (aka KAISER) patches, are going to affect applicatio Read more…

By Rosemary Francis

Momentum Builds for US Exascale

January 9, 2018

2018 looks to be a great year for the U.S. exascale program. The last several months of 2017 revealed a number of important developments that help put the U.S. Read more…

By Alex R. Larzelere

ANL’s Rick Stevens on CANDLE, ARM, Quantum, and More

January 8, 2018

Late last year HPCwire caught up with Rick Stevens, associate laboratory director for computing, environment and life Sciences at Argonne National Laboratory, f Read more…

By John Russell

Inventor Claims to Have Solved Floating Point Error Problem

January 17, 2018

"The decades-old floating point error problem has been solved," proclaims a press release from inventor Alan Jorgensen. The computer scientist has filed for and Read more…

By Tiffany Trader

US Coalesces Plans for First Exascale Supercomputer: Aurora in 2021

September 27, 2017

At the Advanced Scientific Computing Advisory Committee (ASCAC) meeting, in Arlington, Va., yesterday (Sept. 26), it was revealed that the "Aurora" supercompute Read more…

By Tiffany Trader

Japan Unveils Quantum Neural Network

November 22, 2017

The U.S. and China are leading the race toward productive quantum computing, but it's early enough that ultimate leadership is still something of an open questi Read more…

By Tiffany Trader

AMD Showcases Growing Portfolio of EPYC and Radeon-based Systems at SC17

November 13, 2017

AMD’s charge back into HPC and the datacenter is on full display at SC17. Having launched the EPYC processor line in June along with its MI25 GPU the focus he Read more…

By John Russell

Nvidia Responds to Google TPU Benchmarking

April 10, 2017

Nvidia highlights strengths of its newest GPU silicon in response to Google's report on the performance and energy advantages of its custom tensor processor. Read more…

By Tiffany Trader

IBM Begins Power9 Rollout with Backing from DOE, Google

December 6, 2017

After over a year of buildup, IBM is unveiling its first Power9 system based on the same architecture as the Department of Energy CORAL supercomputers, Summit a Read more…

By Tiffany Trader

Fast Forward: Five HPC Predictions for 2018

December 21, 2017

What’s on your list of high (and low) lights for 2017? Volta 100’s arrival on the heels of the P100? Appearance, albeit late in the year, of IBM’s Power9? Read more…

By John Russell

GlobalFoundries Puts Wind in AMD’s Sails with 12nm FinFET

September 24, 2017

From its annual tech conference last week (Sept. 20), where GlobalFoundries welcomed more than 600 semiconductor professionals (reaching the Santa Clara venue Read more…

By Tiffany Trader

Leading Solution Providers

Chip Flaws ‘Meltdown’ and ‘Spectre’ Loom Large

January 4, 2018

The HPC and wider tech community have been abuzz this week over the discovery of critical design flaws that impact virtually all contemporary microprocessors. T Read more…

By Tiffany Trader

Perspective: What Really Happened at SC17?

November 22, 2017

SC is over. Now comes the myriad of follow-ups. Inboxes are filled with templated emails from vendors and other exhibitors hoping to win a place in the post-SC thinking of booth visitors. Attendees of tutorials, workshops and other technical sessions will be inundated with requests for feedback. Read more…

By Andrew Jones

Tensors Come of Age: Why the AI Revolution Will Help HPC

November 13, 2017

Thirty years ago, parallel computing was coming of age. A bitter battle began between stalwart vector computing supporters and advocates of various approaches to parallel computing. IBM skeptic Alan Karp, reacting to announcements of nCUBE’s 1024-microprocessor system and Thinking Machines’ 65,536-element array, made a public $100 wager that no one could get a parallel speedup of over 200 on real HPC workloads. Read more…

By John Gustafson & Lenore Mullin

Delays, Smoke, Records & Markets – A Candid Conversation with Cray CEO Peter Ungaro

October 5, 2017

Earlier this month, Tom Tabor, publisher of HPCwire and I had a very personal conversation with Cray CEO Peter Ungaro. Cray has been on something of a Cinderell Read more…

By Tiffany Trader & Tom Tabor

Flipping the Flops and Reading the Top500 Tea Leaves

November 13, 2017

The 50th edition of the Top500 list, the biannual publication of the world’s fastest supercomputers based on public Linpack benchmarking results, was released Read more…

By Tiffany Trader

GlobalFoundries, Ayar Labs Team Up to Commercialize Optical I/O

December 4, 2017

GlobalFoundries (GF) and Ayar Labs, a startup focused on using light, instead of electricity, to transfer data between chips, today announced they've entered in Read more…

By Tiffany Trader

How Meltdown and Spectre Patches Will Affect HPC Workloads

January 10, 2018

There have been claims that the fixes for the Meltdown and Spectre security vulnerabilities, named the KPTI (aka KAISER) patches, are going to affect applicatio Read more…

By Rosemary Francis

HPC Chips – A Veritable Smorgasbord?

October 10, 2017

For the first time since AMD's ill-fated launch of Bulldozer the answer to the question, 'Which CPU will be in my next HPC system?' doesn't have to be 'Whichever variety of Intel Xeon E5 they are selling when we procure'. Read more…

By Dairsie Latimer

  • arrow
  • Click Here for More Headlines
  • arrow
Share This