This week we were on hand for Intel’s “Rearchitecting the Datacenter” event, which offered a glimpse into how the company imagines its future path along both low power and high performance server routes.
In addition to the announcement of key details around the Atom family and upcoming Avoton and Rangeley, and a general roadmap for the 14nm products expected to roll out in the next few years, the emphasis was on integration between hardware and software. From software defined storage and networks to the role of fabrics in typing together low and super-power cores, the company collected its strategy under a number of nets–one of which was HPC specifically.
While a great deal of the focus was on web-scale and enterprise datacenters, the company’s HPC lead, Raj Hazra, gave a detailed presentation about how new trends can push HPC into a greater “knowledge economy” and into more mainstream (beyond the “traditional” academic and government arenas) contexts.
The recorded presentation reflects Hazra’s wider view of where Intel stands with its high performance computing strategy on a broad level, which was meant for the room’s more mainstream audience. To drill down on specifics, we spent some time chatting with him in more detail about the key concepts he outlined, including power, performance, neo-heterogeneity, integration and the future reach of Xeon Phi into the enterprise.
Hazra emphasized the concept of Intel’s focus on “neo-heterogeneity” in his discussion of where HPC fits into Intel’s larger datacenter strategy going forward. As he defined, this refers to making a new approach to heterogeneity possibly by taking advantage of hardware that’s been designed for different performance (and performance per watt) but which looks unified on the programmer’s side.
The ROI here, he explains, is in providing the capability for users to quickly and easily port an application and then contend about the much longer process of optimization. For users waiting on the long port times to discrete GPUs, he says, it’s a risk as the speedups may or may not be present.
With Xeon Phi, however, he stresses, there is little risk in porting and “trying out” the approach and the optimization process is usually shorter than with GPUs and users find that in the process their codes are optimized for general Xeon as they go. While we’re still on the lookout for a breakdown of some common application types and their GPU to co-processor optimization times (not port–Intel has that time cut down considerably) this does reflect what we’ve heard from Phi and GPU users at TACC, among other centers.
The real test in the coming years for Phi’s reach outside of the government and academic sites is when the ISV community gets behind the co-processor. The initial users in academia and elsewhere generally write their own codes and aren’t reliant on the internal processes of ISV approval and tuning. Once a wide range of commercial codes are conditioned to take advantage of any potential performance benefits, the market for Xeon Phi will be quite large, Hazra anticipates.
And certainly, as with the other items on Intel’s roadmap, the focus is not on niches–it’s on reaching every segment of the server market via ultra-low power approaches fed by developments on the Atom family side all the way up to Phi. The company stressed this week its role in bringing software-defined networking, storage and more integrated compute capabilities to all market segments–and HPC is no exception.
The integration value coming from Intel on this side will be felt when the interconnect assets they’ve pulled in from QLogic and Cray come to bear. On this topic, Hazra says Intel is focused on having a discrete network solution wherein they integrate the network interface control on the processors. From there, he says, “we’ll innovate on what that integrated version is to be able to improve performance, lower power and add features to it so it addresses next-gen programming models.”
In terms of the role of QLogic in particular, he notes, “our goal, and we’re engaged in building the next gen products with integrated fabric and this has to cover the gamut, from high-end HPC to midrange and to the enterprise.”
As one might imagine, the HPC flavor on the Top 500 and academic side was more muted in favor of putting high-end processor technology in greater enterprise context during this general datacenter event. However, the one key topic that tied HPC to the rest of the strategy outline is how the technologies developed in this community can feed a much wider set of general enterprise applications and server approaches. Hazra agreed that big data is indeed a prime way for his HPC group to extend outward, noting that as analytics evolve, the need to blend high performance computing developments (and in general, the role of more robust hardware) with these new algorithms will open up new opportunities.
Big data and, of course, the range of scientific and research applications, are all stoking HPC investments on Intel’s side, Hazra side. Unlike AMD’s recent statement that HPC is relatively low margin, he stressed Intel’s investment in it with a focus on longer-term goals. “The paradigm is that we are going to be continuing to improve compute capacity. Manycore is the way forward. We are investing in it, but the world is still on multicore. Still we’re starting to see leading edges of applications and algorithms that are going to manycore and we expect that to be the way applications s of the future are built so we have to move now instead of being reactive.”
As the company’s senior VP and General Manager of the Datacenter and Connected Systems Group, Diane Bryant, stressed repeatedly, there are converging forces (cloud and big data in particular) that require tighter integration at the storage, network and rack levels. She outlined the company’s Rack Scale Architecture (RSA) which pushes utilization and flexibility for cloud datacenters in particular, and played up the role of low-power, ultra-dense servers for a future that doesn’t just include cloud datacenters or small devices.
Hazra echoed the value of this move, noting that HPC is also diversifying. He says that while the majority of HPC remains under carefully engineered co-design there is no doubt that certain segments of HPC that share the characteristics of low energy scale-out (life sciences, algorithms and apps that fit that scale-out highly dense, low power pattern) represent a trend of overall diversification of system architecture. “It’s the beginning of a curve,” he says, “and Intel wants to be responsive and not reactive.”
We asked Hazra whether or not this steady march to lower power and higher density marks a death of the server industry as we know it, in part because of the event’s emphasis on Open Compute inspired designs and approaches. “I don’t know if it’s a death or rebirth,” he says, but “the open projects bring like minds together and provide a scaffolding to build greater things.” He says that questions about sea changes in the server businesses this aren’t unfamiliar..”In the HPC space at one point, many said the Beowulf clusters would kill HPC, but look at the tremendous amounts of differentiation.”
And that’s just what Intel wants to architect into their strategy–a base that extends across it’s ultra-low power lines all the way up to Phi–and one that lets the OEMs differentiate to create value and differentiation as the lines between what chipmakers traditionally do (and do not do) are blurred.