Intel Hits Refresh on Datacenter Vision

By Nicole Hemsoth

July 26, 2013

This week we were on hand for Intel’s “Rearchitecting the Datacenter” event, which offered a glimpse into how the company imagines its future path along both low power and high performance server routes.

In addition to the announcement of key details around the Atom family and upcoming Avoton and Rangeley, and a general roadmap for the 14nm products expected to roll out in the next few years, the emphasis was on integration between hardware and software. From software defined storage and networks to the role of fabrics in typing together low and super-power cores, the company collected its strategy under a number of nets–one of which was HPC specifically.

While a great deal of the focus was on web-scale and enterprise datacenters, the company’s HPC lead, Raj Hazra, gave a detailed presentation about how new trends can push HPC into a greater “knowledge economy” and into more mainstream (beyond the “traditional” academic and government arenas) contexts.  

The recorded presentation reflects Hazra’s wider view of where Intel stands with its high performance computing strategy on a broad level, which was meant for the room’s more mainstream audience. To drill down on specifics, we spent some time chatting with him in more detail about the key concepts he outlined, including power, performance, neo-heterogeneity, integration and the future reach of Xeon Phi into the enterprise. 

Hazra emphasized the concept of Intel’s focus on “neo-heterogeneity” in his discussion of where HPC fits into Intel’s larger datacenter strategy going forward. As he defined, this refers to making a new approach to heterogeneity possibly by taking advantage of hardware that’s been designed for different performance (and performance per watt) but which looks unified on the programmer’s side.  

The ROI here, he explains, is in providing the capability for users to quickly and easily port an application and then contend about the much longer process of optimization. For users waiting on the long port times to discrete GPUs, he says, it’s a risk as the speedups may or may not be present.

With Xeon Phi, however, he stresses, there is little risk in porting and “trying out” the approach and the optimization process is usually shorter than with GPUs and users find that in the process their codes are optimized for general Xeon as they go. While we’re still on the lookout for a breakdown of some common application types and their GPU to co-processor optimization times (not port–Intel has that time cut down considerably) this does reflect what we’ve heard from Phi and GPU users at TACC, among other centers.

The real test in the coming years for Phi’s reach outside of the government and academic sites is when the ISV community gets behind the co-processor. The initial users in academia and elsewhere generally write their own codes and aren’t reliant on the internal processes of ISV approval and tuning. Once a wide range of commercial codes are conditioned to take advantage of any potential performance benefits, the market for Xeon Phi will be quite large, Hazra anticipates.

And certainly, as with the other items on Intel’s roadmap, the focus is not on niches–it’s on reaching every segment of the server market via ultra-low power approaches fed by developments on the Atom family side all the way up to Phi. The company stressed this week its role in bringing software-defined networking, storage and more integrated compute capabilities to all market segments–and HPC is no exception.

The integration value coming from Intel on this side will be felt when the interconnect assets they’ve pulled in from QLogic and Cray come to bear. On this topic, Hazra says Intel is focused on having a discrete network solution wherein they integrate the network interface control on the processors. From there, he says, “we’ll innovate on what that integrated version is to be able to improve performance, lower power and add features to it so it addresses next-gen programming models.”

In terms of the role of QLogic in particular, he notes, “our goal, and we’re engaged in building the next gen products with integrated fabric and this has to cover the gamut, from high-end HPC to midrange and to the enterprise.”

As one might imagine, the HPC flavor on the Top 500 and academic side was more muted in favor of putting high-end processor technology in greater enterprise context during this general datacenter event. However, the one key topic that tied HPC to the rest of the strategy outline is how the technologies developed in this community can feed a much wider set of general enterprise applications and server approaches. Hazra agreed that big data is indeed a prime way for his HPC group to extend outward, noting that as analytics evolve, the need to blend high performance computing developments (and in general, the role of more robust hardware) with these new algorithms will open up new opportunities.

Big data and, of course, the range of scientific and research applications, are all stoking HPC investments on Intel’s side, Hazra side. Unlike AMD’s recent statement that HPC is relatively low margin, he stressed Intel’s investment in it with a focus on longer-term goals. “The paradigm is that we are going to be continuing to improve compute capacity. Manycore is the way forward.  We are investing in it, but the world is still on multicore. Still we’re starting to see leading edges of  applications and algorithms that are going to manycore and we expect that to be the way applications s of the future are built so we have to move now instead of being reactive.”

As the company’s senior VP and General Manager of the Datacenter and Connected Systems Group, Diane Bryant, stressed repeatedly, there are converging forces (cloud and big data in particular) that require tighter integration at the storage, network and rack levels. She outlined the company’s Rack Scale Architecture (RSA) which pushes utilization and flexibility for cloud datacenters in particular, and played up the role of low-power, ultra-dense servers for a future that doesn’t just include cloud datacenters or small devices.

Hazra echoed the value of this move, noting that HPC is also diversifying. He says that while the majority of HPC remains under carefully engineered co-design there is no doubt that certain segments of HPC that share the characteristics of low energy scale-out (life sciences, algorithms and apps that fit that scale-out highly dense, low power pattern) represent a trend of overall diversification of system architecture. “It’s the beginning of a curve,” he says, “and Intel wants to be responsive and not reactive.”

We asked Hazra whether or not this steady march to lower power and higher density marks a death of the server industry as we know it, in part because of the event’s emphasis on Open Compute inspired designs and approaches. “I don’t know if it’s a death or rebirth,” he says, but “the open projects bring like minds together and provide a scaffolding to build greater things.” He says that questions about sea changes in the server businesses this aren’t unfamiliar..”In the HPC space at one point, many said the Beowulf clusters would kill HPC, but look at the tremendous amounts of differentiation.”

And that’s just what Intel wants to architect into their strategy–a base that extends across it’s ultra-low power lines all the way up to Phi–and one that lets the OEMs differentiate to create value and differentiation as the lines between what chipmakers traditionally do (and do not do) are blurred.




Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

Machine Learning at HPC User Forum: Drilling into Specific Use Cases

September 22, 2017

The 66th HPC User Forum held September 5-7, in Milwaukee, Wisconsin, at the elegant and historic Pfister Hotel, highlighting the 1893 Victorian décor and art of “The Grand Hotel Of The West,” contrasted nicely with Read more…

By Arno Kolster

Google Cloud Makes Good on Promise to Add Nvidia P100 GPUs

September 21, 2017

Google has taken down the notice on its cloud platform website that says Nvidia Tesla P100s are “coming soon.” That's because the search giant has announced the beta launch of the high-end P100 Nvidia Tesla GPUs on t Read more…

By George Leopold

Cray Wins $48M Supercomputer Contract from KISTI

September 21, 2017

It was a good day for Cray which won a $48 million contract from the Korea Institute of Science and Technology Information (KISTI) for a 128-rack CS500 cluster supercomputer. The new system, equipped with Intel Xeon Scal Read more…

By John Russell

HPE Extreme Performance Solutions

HPE Prepares Customers for Success with the HPC Software Portfolio

High performance computing (HPC) software is key to harnessing the full power of HPC environments. Development and management tools enable IT departments to streamline installation and maintenance of their systems as well as create, optimize, and run their HPC applications. Read more…

Adolfy Hoisie to Lead Brookhaven’s Computing for National Security Effort

September 21, 2017

Brookhaven National Laboratory announced today that Adolfy Hoisie will chair its newly formed Computing for National Security department, which is part of Brookhaven’s new Computational Science Initiative (CSI). Read more…

By John Russell

Machine Learning at HPC User Forum: Drilling into Specific Use Cases

September 22, 2017

The 66th HPC User Forum held September 5-7, in Milwaukee, Wisconsin, at the elegant and historic Pfister Hotel, highlighting the 1893 Victorian décor and art o Read more…

By Arno Kolster

Stanford University and UberCloud Achieve Breakthrough in Living Heart Simulations

September 21, 2017

Cardiac arrhythmia can be an undesirable and potentially lethal side effect of drugs. During this condition, the electrical activity of the heart turns chaotic, Read more…

By Wolfgang Gentzsch, UberCloud, and Francisco Sahli, Stanford University

PNNL’s Center for Advanced Tech Evaluation Seeks Wider HPC Community Ties

September 21, 2017

Two years ago the Department of Energy established the Center for Advanced Technology Evaluation (CENATE) at Pacific Northwest National Laboratory (PNNL). CENAT Read more…

By John Russell

Exascale Computing Project Names Doug Kothe as Director

September 20, 2017

The Department of Energy’s Exascale Computing Project (ECP) has named Doug Kothe as its new director effective October 1. He replaces Paul Messina, who is stepping down after two years to return to Argonne National Laboratory. Kothe is a 32-year veteran of DOE’s National Laboratory System. Read more…

Takeaways from the Milwaukee HPC User Forum

September 19, 2017

Milwaukee’s elegant Pfister Hotel hosted approximately 100 attendees for the 66th HPC User Forum (September 5-7, 2017). In the original home city of Pabst Blu Read more…

By Merle Giles

Kathy Yelick Charts the Promise and Progress of Exascale Science

September 15, 2017

On Friday, Sept. 8, Kathy Yelick of Lawrence Berkeley National Laboratory and the University of California, Berkeley, delivered the keynote address on “Breakthrough Science at the Exascale” at the ACM Europe Conference in Barcelona. In conjunction with her presentation, Yelick agreed to a short Q&A discussion with HPCwire. Read more…

By Tiffany Trader

DARPA Pledges Another $300 Million for Post-Moore’s Readiness

September 14, 2017

The Defense Advanced Research Projects Agency (DARPA) launched a giant funding effort to ensure the United States can sustain the pace of electronic innovation vital to both a flourishing economy and a secure military. Under the banner of the Electronics Resurgence Initiative (ERI), some $500-$800 million will be invested in post-Moore’s Law technologies. Read more…

By Tiffany Trader

IBM Breaks Ground for Complex Quantum Chemistry

September 14, 2017

IBM has reported the use of a novel algorithm to simulate BeH2 (beryllium-hydride) on a quantum computer. This is the largest molecule so far simulated on a quantum computer. The technique, which used six qubits of a seven-qubit system, is an important step forward and may suggest an approach to simulating ever larger molecules. Read more…

By John Russell

How ‘Knights Mill’ Gets Its Deep Learning Flops

June 22, 2017

Intel, the subject of much speculation regarding the delayed, rewritten or potentially canceled “Aurora” contract (the Argonne Lab part of the CORAL “ Read more…

By Tiffany Trader

Reinders: “AVX-512 May Be a Hidden Gem” in Intel Xeon Scalable Processors

June 29, 2017

Imagine if we could use vector processing on something other than just floating point problems.  Today, GPUs and CPUs work tirelessly to accelerate algorithms Read more…

By James Reinders

NERSC Scales Scientific Deep Learning to 15 Petaflops

August 28, 2017

A collaborative effort between Intel, NERSC and Stanford has delivered the first 15-petaflops deep learning software running on HPC platforms and is, according Read more…

By Rob Farber

Oracle Layoffs Reportedly Hit SPARC and Solaris Hard

September 7, 2017

Oracle’s latest layoffs have many wondering if this is the end of the line for the SPARC processor and Solaris OS development. As reported by multiple sources Read more…

By John Russell

Six Exascale PathForward Vendors Selected; DoE Providing $258M

June 15, 2017

The much-anticipated PathForward awards for hardware R&D in support of the Exascale Computing Project were announced today with six vendors selected – AMD Read more…

By John Russell

Top500 Results: Latest List Trends and What’s in Store

June 19, 2017

Greetings from Frankfurt and the 2017 International Supercomputing Conference where the latest Top500 list has just been revealed. Although there were no major Read more…

By Tiffany Trader

IBM Clears Path to 5nm with Silicon Nanosheets

June 5, 2017

Two years since announcing the industry’s first 7nm node test chip, IBM and its research alliance partners GlobalFoundries and Samsung have developed a proces Read more…

By Tiffany Trader

Nvidia Responds to Google TPU Benchmarking

April 10, 2017

Nvidia highlights strengths of its newest GPU silicon in response to Google's report on the performance and energy advantages of its custom tensor processor. Read more…

By Tiffany Trader

Leading Solution Providers

Graphcore Readies Launch of 16nm Colossus-IPU Chip

July 20, 2017

A second $30 million funding round for U.K. AI chip developer Graphcore sets up the company to go to market with its “intelligent processing unit” (IPU) in Read more…

By Tiffany Trader

Google Releases Deeplearn.js to Further Democratize Machine Learning

August 17, 2017

Spreading the use of machine learning tools is one of the goals of Google’s PAIR (People + AI Research) initiative, which was introduced in early July. Last w Read more…

By John Russell

Russian Researchers Claim First Quantum-Safe Blockchain

May 25, 2017

The Russian Quantum Center today announced it has overcome the threat of quantum cryptography by creating the first quantum-safe blockchain, securing cryptocurrencies like Bitcoin, along with classified government communications and other sensitive digital transfers. Read more…

By Doug Black

Google Debuts TPU v2 and will Add to Google Cloud

May 25, 2017

Not long after stirring attention in the deep learning/AI community by revealing the details of its Tensor Processing Unit (TPU), Google last week announced the Read more…

By John Russell

EU Funds 20 Million Euro ARM+FPGA Exascale Project

September 7, 2017

At the Barcelona Supercomputer Centre on Wednesday (Sept. 6), 16 partners gathered to launch the EuroEXA project, which invests €20 million over three-and-a-half years into exascale-focused research and development. Led by the Horizon 2020 program, EuroEXA picks up the banner of a triad of partner projects — ExaNeSt, EcoScale and ExaNoDe — building on their work... Read more…

By Tiffany Trader

Amazon Debuts New AMD-based GPU Instances for Graphics Acceleration

September 12, 2017

Last week Amazon Web Services (AWS) streaming service, AppStream 2.0, introduced a new GPU instance called Graphics Design intended to accelerate graphics. The Read more…

By John Russell

Cray Moves to Acquire the Seagate ClusterStor Line

July 28, 2017

This week Cray announced that it is picking up Seagate's ClusterStor HPC storage array business for an undisclosed sum. "In short we're effectively transitioning the bulk of the ClusterStor product line to Cray," said CEO Peter Ungaro. Read more…

By Tiffany Trader

GlobalFoundries: 7nm Chips Coming in 2018, EUV in 2019

June 13, 2017

GlobalFoundries has formally announced that its 7nm technology is ready for customer engagement with product tape outs expected for the first half of 2018. The Read more…

By Tiffany Trader

  • arrow
  • Click Here for More Headlines
  • arrow
Share This