Many Cores, Large Memory, Low Latency Memory Access – Numascale Shows a New Way

By Nicole Hemsoth

September 30, 2013

Shared Memory – Cluster Price

The big differentiator for Numascale’s interconnect, NumaConnect, compared to other high-speed interconnect technologies is the shared memory and cache coherency. These features allow programs to access any memory location and any memory mapped I/O device in a multiprocessor system with high degree of efficiency. It provides scalable systems with a unified programming model that stays the same from the small multi-core machines used in laptops and desktops to the largest imaginable single system image machines that may contain thousands of processors. The architecture is commonly classified as ccNuma or Numa but the interconnect system can alternatively be used as low latency clustering interconnect.

The most prominent advantages that NumaConnect offers are:

  • NumaConnect offers true and transparent cache coherent shared memory NumaConnectimplemented in hardware at cluster price. Probably the most affordable large shared memory solution around.
  • NumaConnect offers the largest shared memory available today. The hardware can utilize a 256TB addressing space and no memory is lost to buffering of copies of remote memories.
  • It is a general conception that the shared memory model makes parallel programming easier than the clustering or message passing model. Parallel programming will probably never become really easy, so any simplification should be welcome. Thousands of years of work have been put into parallelizing software for clusters, and these applications will probably be running on clusters for a while. Applications that have not been moved to clusters or that are difficult to parallelize for message passing will benefit greatly from Numascale’s offering.
  • In the memory mapped I/O scheme of x86 servers all I/O devices will automatically be shared and all I/O devices in all boxes are directly available from any thread of the OS or application.
  • Numascale runs a plain standard OS with some minor add-ons to the standard Linux kernel, while some kernel parameters should preferably be optimized for the OS to run well on a large number of cores.
  • With NumaConnect the system can run a single image OS. This greatly simplifies the tasks of system maintenance and operation. In a very large system a highly reduced number of OSes can be used.
  • No virtualization software is needed to the NumaConnect systems. Virtualization systems tend to be large, large and complicated system software is not bug free and introduces execution overhead.

As compared to some emulation systems for large memories we think NumaConnect excels by:

  • The cache line level coherency that cannot be exploited by software systems gives much lower probability for false sharing. A cache line is 64 bytes and the pages that will be used for software systems are 4KBytes or 2Mbytes.
  • The system software has optimizations for cache line false sharing since this happens on standard multi-socket servers as well.
  • Buffer space for remote pages in software systems may consume as much as 25% of the memory and NumaConnect do not use any buffers in memory.
  • NumaConnect shows very good performance for random access in large data areas.

Integration in Commodity Servers

The Numascale systems are deployed by installing a card with PCI form factor into a standard server. This approach makes it possible to take advantage of the great price break of mass produced servers with volume applications outside the segment that NumaConnect covers. Serves from IBM and Supermicro are favored today and provide excellent building blocks for large memory systems in combination with the NumaConnect Cards.

Numascale servers

Designed for Scalability and Robustness

The design is implemented in a chip, NumaChip, produced by IBM Microelectronics. The chip holds all functions of the interconnect except the NumaCache, a cache for accesses from one node to its companion nodes in the system, where standard external DRAM modules are used.

NumaChip implements 12 bits for the physical node address, limiting the number of nodes in a single image system to 4,096. Each node can have multiple processor cores. The AMD processors can address 256TBytes of data and this limits total memory space of the systems.

Functionality is included to manage robustness issues associated with high node counts and extremely high requirements for data integrity with the ability to provide high availability for systems managing critical data in transaction processing and real-time control.

A directory based cache coherence protocol handles scaling with significant number of nodes sharing data to avoid overloading of the interconnect between nodes with coherency traffic which would seriously reduce real data throughput. 

The basic ring topology with distributed switching allows a number of different interconnect configurations that are more scalable than most other interconnect switch fabrics. This also eliminates the need for a centralized switch and includes inherent redundancy for multidimensional topologies. 

Integrated, distributed switching

The NumaChip contains an on-chip switch to connect to other nodes in a NumaChip based system and eliminating the need to use a centralized switch. The on-chip switch can connect systems in one, two or three dimensions. Small systems can use one, medium sized system two and large systems will use all three dimensions to provide efficient and scalable connectivity between processors.

The two- and three-dimensional topologies (torus) that have the advantage of built-in redundancy as opposed to systems based on centralized switches, where the switch represents a single point of failure.

The distributed switching reduces the cost of the system since there is no extra switch hardware to pay for. It also reduces the amount of rack space required to hold the system as well as the power consumption and heat dissipation from the switch hardware and the associated power supply energy loss.


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