A Path to Many-Task Computing on the Xeon Phi

By Tiffany Trader

October 24, 2013

It’s been nearly a year since the Intel Xeon Phi Coprocessor debuted at SC12, and in that time, it has experienced strong acceptance from the community. But as this is a relatively new technology, research into its usefulness is still forthcoming.

Adding to the growing body of research on the Phi is “Understanding the Costs of Many-Task Computing Workloads on Intel Xeon Phi Coprocessors,” written by a team of Illinois-based computer scientists and presented at the 2nd Greater Chicago Area System Research Workshop (GCASR) in May 2013.

The paper focuses on the opportunities for Many-Task Computing (MTC) to leverage the Intel Xeon Phi architecture. The programming paradigm that is Many-Task Computing (MTC) serves as a bridge between high-performance computing (HPC) and high-throughput computing (HTC). As the name implies, Many-Task Computing reflects the practice of running many computational tasks (dependent or independent) over a brief period of time. In MTC, metrics are most often measured in seconds (i.e., FLOPS, tasks/s, MB/s I/O rates), as opposed to operations (i.e., jobs) per month.

The impetus for the endeavor was explained thusly by the research team: “MTC has been well supported on Clouds, Grids, and Supercomputers on traditional computing architectures, but the abundance of hybrid large-scale systems using accelerators has motivated us to explore the support of MTC on the new Intel Xeon Phi accelerators.”

The crux of the researchers’ proposal is the creation of a new framework that “provides fine granularity for executing MTC applications across large scale compute clusters.” Integrating this capability into their existing graphics card framework, GeMTC, would “provide transparent access to GPUs, Xeon Phis, and future generations of accelerators to help bridge the gap into Exascale computing.”

The Intel Xeon Phi chip, aimed at highly parallel number-crunching, is the first product of Intel’s Many Integrated Core (MIC) architecture. In simple terms, the Phi coprocessor is an x86 based processor glued onto a PCIe 8x expansion card. The chip sports 60 cores, 4x hyper-threaded, for a total of 240 hardware threads, and stuffs just over 1 teraflop of double-precision performance in a single accelerator.

The first petascale adoption of Intel Xeon Phi coprocessors is Texas Advanced Computing Center’s Stampede system, which leverages 6,880 of these chips to arrive at 7.4 additional petaflops of peak computational performance. One of the most powerful supercomputers in the world, Stampede tops out at a total peak performance of 9.6 petaflops.

The paper seeks to provide a deep understanding of MTC on the Intel Xeon Phi architecture. The researchers test the performance of several different workloads using pre-production Intel Xeon Phi hardware and the Intel-provided SCIF protocol for communicating across the PCI-Express bus. With this setup, they achieve over 90 percent efficiency, a result that is close to or better than using OpenMP for offloading tasks over 300 uS.

Fig. 1: Efficiency of offloading 128 tasks to Xeon Phi. Comparison between OpenMP and SCIF with individual offloads and batch offloads.
Fig. 1: Efficiency of offloading 128 tasks to Xeon Phi.
Comparison between OpenMP and SCIF with individual
offloads and batch offloads.

They write: “This performance opens the opportunity for the development of a framework for executing heterogeneous tasks on the Xeon Phi alongside other potential accelerators including graphics cards for MTC applications.”

The Intel Xeon Phi coprocessor is similar to other hardware accelerators such as general-purpose GPUs (GPGPUs) but there are important distinctions. Graphics cards, specifically GPGPUs, have become a popular means of providing parallelism for HPC applications. But extracting performance gains from GPUs means a retooling of the code, which can be time-consuming and requires considerable expertise. The claim from Intel is that the Phi provides a more familiar environment, which makes it easier to program.

The experiment employed a pre-production Xeon Phi – a 61-core version featuring 8GB of GDDR5 connected to the host via a PCI Express bus. One of these cores is reserved for the Linux OS. The authors note that with this platform, “it is possible to use OpenMP, POSIX threads, OpenCL, Intel Math Kernel Library, MPI, or other popular libraries to develop and offload applications to the accelerator.”

When the researchers compared the efficiency of offloading 128 tasks to Xeon Phi between OpenMP and SCIF with individual offloads and batch offloads, they found that jobs over 320 uS benefit from the SCIF framework when sent in this length of a batch with performance that was slightly above OpenMP.

The experiment shows it’s possible to achieve minimum overhead with the Xeon Phi by directly communicating between the host and accelerator via SCIF across the PCI Express bus. The preliminary results suggest that under the authors’ proposed framework, “the resources of a Xeon Phi could be shared across multiple processes and users in a large scale computing environment while maintaining high performance through the use of specialized microkernels.”

Just like GeMTC, the new framework would include three types off operations: Push/Poll for sending and receiving jobs, Malloc/Free for preparing device memory, and a memory copy operation to copy data to or from the accelerator. A tie-in to Swift/T could be used for multi-node configurations.

In the future, the research team will turn their attention to using the Phi for other science codes, including Molecular Dynamics applications, Protein Simulators and more.

Authors on this paper include Jeffrey Johnson, Scott J. Krieder, Benjamin Grimmer – all from the Illinois Institute of Technology – and Justin M. Wozniak (from Argonne National Laboratory), Michael Wilde (Argonne and the University of Chicago) and Ioan Raicu (Illinois Institute of Technology and the University of Chicago).

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

Pfizer HPC Engineer Aims to Automate Software Stack Testing

January 17, 2019

Seeking to reign in the tediousness of manual software testing, Pfizer HPC Engineer Shahzeb Siddiqui is developing an open source software tool called buildtest, aimed at automating software stack testing by providing the community with a central repository of tests for common HPC apps and the ability to automate execution of testing. Read more…

By Tiffany Trader

Senegal Prepares to Take Delivery of Atos Supercomputer

January 16, 2019

In just a few months time, Senegal will be operating the second largest HPC system in sub-Saharan Africa. The Minister of Higher Education, Research and Innovation Mary Teuw Niane made the announcement on Monday (Jan. 14 Read more…

By Tiffany Trader

Google Cloud Platform Extends GPU Instance Options

January 16, 2019

If it's Nvidia GPUs you're after to power your AI/HPC/visualization workload, Google Cloud has them, now claiming "broadest GPU availability." Each of the three big public cloud vendors has by turn touted the latest and Read more…

By Tiffany Trader

HPE Extreme Performance Solutions

HPE Systems With Intel Omni-Path: Architected for Value and Accessible High-Performance Computing

Today’s high-performance computing (HPC) and artificial intelligence (AI) users value high performing clusters. And the higher the performance that their system can deliver, the better. Read more…

IBM Accelerated Insights

Resource Management in the Age of Artificial Intelligence

New challenges demand fresh approaches

Fueled by GPUs, big data, and rapid advances in software, the AI revolution is upon us. Read more…

STAC Floats ML Benchmark for Financial Services Workloads

January 16, 2019

STAC (Securities Technology Analysis Center) recently released an ‘exploratory’ benchmark for machine learning which it hopes will evolve into a firm benchmark or suite of benchmarking tools to compare the performanc Read more…

By John Russell

Google Cloud Platform Extends GPU Instance Options

January 16, 2019

If it's Nvidia GPUs you're after to power your AI/HPC/visualization workload, Google Cloud has them, now claiming "broadest GPU availability." Each of the three Read more…

By Tiffany Trader

STAC Floats ML Benchmark for Financial Services Workloads

January 16, 2019

STAC (Securities Technology Analysis Center) recently released an ‘exploratory’ benchmark for machine learning which it hopes will evolve into a firm benchm Read more…

By John Russell

A Big Data Journey While Seeking to Catalog our Universe

January 16, 2019

It turns out, astronomers have lots of photos of the sky but seek knowledge about what the photos mean. Sound familiar? Big data problems are often characterize Read more…

By James Reinders

Intel Bets Big on 2-Track Quantum Strategy

January 15, 2019

Quantum computing has lived so long in the future it’s taken on a futuristic life of its own, with a Gartner-style hype cycle that includes triggers of innovation, inflated expectations and – though a useful quantum system is still years away – anticipatory troughs of disillusionment. Read more…

By Doug Black

IBM Quantum Update: Q System One Launch, New Collaborators, and QC Center Plans

January 10, 2019

IBM made three significant quantum computing announcements at CES this week. One was introduction of IBM Q System One; it’s really the integration of IBM’s Read more…

By John Russell

IBM’s New Global Weather Forecasting System Runs on GPUs

January 9, 2019

Anyone who has checked a forecast to decide whether or not to pack an umbrella knows that weather prediction can be a mercurial endeavor. It is a Herculean task: the constant modeling of incredibly complex systems to a high degree of accuracy at a local level within very short spans of time. Read more…

By Oliver Peckham

The Case Against ‘The Case Against Quantum Computing’

January 9, 2019

It’s not easy to be a physicist. Richard Feynman (basically the Jimi Hendrix of physicists) once said: “The first principle is that you must not fool yourse Read more…

By Ben Criger

The Deep500 – Researchers Tackle an HPC Benchmark for Deep Learning

January 7, 2019

How do you know if an HPC system, particularly a larger-scale system, is well-suited for deep learning workloads? Today, that’s not an easy question to answer Read more…

By John Russell

Quantum Computing Will Never Work

November 27, 2018

Amid the gush of money and enthusiastic predictions being thrown at quantum computing comes a proposed cold shower in the form of an essay by physicist Mikhail Read more…

By John Russell

Cray Unveils Shasta, Lands NERSC-9 Contract

October 30, 2018

Cray revealed today the details of its next-gen supercomputing architecture, Shasta, selected to be the next flagship system at NERSC. We've known of the code-name "Shasta" since the Argonne slice of the CORAL project was announced in 2015 and although the details of that plan have changed considerably, Cray didn't slow down its timeline for Shasta. Read more…

By Tiffany Trader

AMD Sets Up for Epyc Epoch

November 16, 2018

It’s been a good two weeks, AMD’s Gary Silcott and Andy Parma told me on the last day of SC18 in Dallas at the restaurant where we met to discuss their show news and recent successes. Heck, it’s been a good year. Read more…

By Tiffany Trader

The Case Against ‘The Case Against Quantum Computing’

January 9, 2019

It’s not easy to be a physicist. Richard Feynman (basically the Jimi Hendrix of physicists) once said: “The first principle is that you must not fool yourse Read more…

By Ben Criger

US Leads Supercomputing with #1, #2 Systems & Petascale Arm

November 12, 2018

The 31st Supercomputing Conference (SC) - commemorating 30 years since the first Supercomputing in 1988 - kicked off in Dallas yesterday, taking over the Kay Ba Read more…

By Tiffany Trader

Contract Signed for New Finnish Supercomputer

December 13, 2018

After the official contract signing yesterday, configuration details were made public for the new BullSequana system that the Finnish IT Center for Science (CSC Read more…

By Tiffany Trader

Nvidia’s Jensen Huang Delivers Vision for the New HPC

November 14, 2018

For nearly two hours on Monday at SC18, Jensen Huang, CEO of Nvidia, presented his expansive view of the future of HPC (and computing in general) as only he can do. Animated. Backstopped by a stream of data charts, product photos, and even a beautiful image of supernovae... Read more…

By John Russell

HPE No. 1, IBM Surges, in ‘Bucking Bronco’ High Performance Server Market

September 27, 2018

Riding healthy U.S. and global economies, strong demand for AI-capable hardware and other tailwind trends, the high performance computing server market jumped 28 percent in the second quarter 2018 to $3.7 billion, up from $2.9 billion for the same period last year, according to industry analyst firm Hyperion Research. Read more…

By Doug Black

Leading Solution Providers

SC 18 Virtual Booth Video Tour

Advania @ SC18 AMD @ SC18
ASRock Rack @ SC18
DDN Storage @ SC18
HPE @ SC18
IBM @ SC18
Lenovo @ SC18 Mellanox Technologies @ SC18
NVIDIA @ SC18
One Stop Systems @ SC18
Oracle @ SC18 Panasas @ SC18
Supermicro @ SC18 SUSE @ SC18 TYAN @ SC18
Verne Global @ SC18

Summit Supercomputer is Already Making its Mark on Science

September 20, 2018

Summit, now the fastest supercomputer in the world, is quickly making its mark in science – five of the six finalists just announced for the prestigious 2018 Read more…

By John Russell

HPC Reflections and (Mostly Hopeful) Predictions

December 19, 2018

So much ‘spaghetti’ gets tossed on walls by the technology community (vendors and researchers) to see what sticks that it is often difficult to peer through Read more…

By John Russell

Intel Confirms 48-Core Cascade Lake-AP for 2019

November 4, 2018

As part of the run-up to SC18, taking place in Dallas next week (Nov. 11-16), Intel is doling out info on its next-gen Cascade Lake family of Xeon processors, specifically the “Advanced Processor” version (Cascade Lake-AP), architected for high-performance computing, artificial intelligence and infrastructure-as-a-service workloads. Read more…

By Tiffany Trader

Germany Celebrates Launch of Two Fastest Supercomputers

September 26, 2018

The new high-performance computer SuperMUC-NG at the Leibniz Supercomputing Center (LRZ) in Garching is the fastest computer in Germany and one of the fastest i Read more…

By Tiffany Trader

Houston to Field Massive, ‘Geophysically Configured’ Cloud Supercomputer

October 11, 2018

Based on some news stories out today, one might get the impression that the next system to crack number one on the Top500 would be an industrial oil and gas mon Read more…

By Tiffany Trader

Microsoft to Buy Mellanox?

December 20, 2018

Networking equipment powerhouse Mellanox could be an acquisition target by Microsoft, according to a published report in an Israeli financial publication. Microsoft has reportedly gone so far as to engage Goldman Sachs to handle negotiations with Mellanox. Read more…

By Doug Black

The Deep500 – Researchers Tackle an HPC Benchmark for Deep Learning

January 7, 2019

How do you know if an HPC system, particularly a larger-scale system, is well-suited for deep learning workloads? Today, that’s not an easy question to answer Read more…

By John Russell

House Passes $1.275B National Quantum Initiative

September 17, 2018

Last Thursday the U.S. House of Representatives passed the National Quantum Initiative Act (NQIA) intended to accelerate quantum computing research and developm Read more…

By John Russell

  • arrow
  • Click Here for More Headlines
  • arrow
Do NOT follow this link or you will be banned from the site!
Share This