Fair Pricing Key to Node Sharing in HPC

By Alex Breslow, University of California San Diego

November 13, 2013

In HPC systems, jobs almost never share compute nodes. Each user requests the number of physical machines that they need to run their job, and then they run it in isolation.

While this practice was clearly the best choice for distributed applications in the pre-multi core era, the same is not necessarily true for the compute nodes of today, which integrate tens to hundreds of cores. Instead, distributed application co-location, whereby multiple parallel codes share the cores on sets of compute nodes, is a pragmatic choice for those seeking to optimize machine performance and power efficiency.

A previous study we did demonstrated co-locating pairs of 1024 process MPI jobs across 2048 cores decreases the run time of most applications and thus improves system throughput and energy efficiency by 10 to 20%.

Figure 1: An example of running 2 two-node jobs in isolation versus co-located: Switching from isolation (left) to co-location (right), where each socket is divided between applications improves system performance and energy efficiency.
Figure 1: An example of running 2 two-node jobs in isolation versus co-located: Switching from isolation (left) to co-location (right), where each socket is divided between applications improves system performance and energy efficiency.

However, not all applications benefit from distributed co-location: a significant number do slow down due to contention from their co-runners. While this slowdown is almost universally offset by gains in the performance of the co-running applications, and therefore still results in improved throughput, it causes an unfair inequity in pricing.This unfairness arises from the typical HPC accounting policy, which charges users proportionally to application run time. An example of this pricing unfairness is shown in Figure 2.  The plot shows the price a user running the GTC code would expect to pay when their job is co-run with each of the applications on the x-axis.  Under the current pricing model, the user would pay 60% more when their job is co-run with MILC instead of with AMG.

Figure 2: The current pricing mechanism (SOP) penalizes the user for co-locating their job by charging them more when their job degrades more.
Figure 2: The current pricing mechanism (SOP) penalizes the user for co-locating their job by charging them more when their job degrades more.

In this current pricing scheme, the user not only suffers from a decrease in utility caused by the increased job run time, but also faces an additional associated surcharge.  Our work, published and to be presented at SC’13 as one of the best paper candidates, targets this problem and introduces contention-aware fair pricing, where a user pays progressively less and less as their job is degraded more and more.

However, implementing such a policy is a challenge, as it requires a non-intrusive mechanism that precisely quantifies individual application degradation caused by co-running applications.  While previous work has employed offline profiling techniques to determine this degradation, we argue that such techniques are not always practical in a production setting, where online application behavior can significantly deviate from offline characterizations [3-6].  Instead we need a dynamic, lightweight, runtime system or OS service to detect such contention.

To satisfy these objectives, we have developed a low-overhead daemon, the Persistent Online Precise Pricing Agent (POPPA).  POPPA uses a fine-grain precise pricing shutter, a novel mechanism capable of measuring contention between applications with less than 1% overhead and with a mean absolute prediction error of 4%.  The shutter mechanism works by alternating the execution environment of each application between one where contention from co-runners is present, and one where it is effectively absent.  POPPA achieves this by cyclically pausing all but one application in a round-robin fashion and measuring the spike in the performance of the lone running application versus when it was co-located.

Figure 3: POPPA alternates application execution between isolation and co-location.  P and S are tunable parameters.
Figure 3: POPPA alternates application execution between isolation and co-location. P and S are tunable parameters.

The above shows the mechanism in action.  During the first phase, the POPPA daemon is dormant and threads from both applications execute.  Next, the instructions per cycle (IPC) of each application is derived from measurements taken using the hardware’s performance monitoring unit.  Then Job B is put to sleep, and the IPC of the Job A is measured.  Then Job B is woken up, and the IPC of both applications is measured.  This process then repeats but with Jobs A and B switching roles.

The POPPA daemon is fully parameterizable to allow for machine- and application-specific tradeoffs. In particular, we can configure the length of the periods between shutter events, the length of the shutter time, as well as the length for pre- and post-shutter measurements. Since each shutter requires all applications but one to sleep, the sleeping applications cannot make progress and thus lose performance during the shutter, which results in run time overhead.  By controlling the ratio between shutter time and shutter interval, this overhead can be carefully tuned to an acceptable value.  For our work, we decided on a shutter interval of 200 ms and a shutter length of 3.2 ms, as these values offered high prediction accuracy while keeping the average overhead under 1%.

This mechanism allows POPPA to be highly accurate, with a mean absolute error of 4%. The low prediction error stems from the fact that the system does not rely on a single measurement for determining degradation estimates, but rather can base its analysis on hundreds to thousands of fine-grain measurements that are uniformly spaced throughout the execution of each co-running application.  As a result, POPPA detects phase-level behaviors in applications that allow it to construct more accurate prediction estimates.

Based on these predictions, we then implement a fair pricing strategy and discount the user relative to their predicted degradation due to co-runner interference.  Our philosophy is that when a user’s application is degraded by 20%, the simplest and most intuitive pricing policy is to discount that user by 20%.  This policy allows the user to easily reason about how they will be priced and to also reap the benefit of a discount, which directly compensates for the additional time taken to run their job.  This compensation encourages users to embrace co-location, as the discounts allow their resource allocation to go further.

The art of precise and fair pricing is a key for designing future, agile, software systems and opens the door to new ways to utilize the rising class of multi- and many-core nodes.  If this article has piqued your interest, we invite you to our talk at the SC’13 conference (Title: “Enabling Fair Pricing on HPC Systems with Node Sharing”, to be presented on November 20th at 10:30AM in rooms 401/402/403). The contact author for this work is Alex Breslow, PhD student at the University of California San Diego.  Ananta Tiwari and Laura Carrington are research scientists at San Diego Supercomputer Center, Martin Schulz is a computer scientist at Lawrence Livermore National Laboratory, and  Lingjia Tang and Jason Mars are assistant professors in the University of Michigan EECS Department.

See Also:

 Cache pirating: Measuring the Curse of the Shared Cache. In Parallel Processing (ICPP)

Quantifying Effects of Shared On-chip Resource Interference for Consolidated Virtual Machines

Bubble-up: Increasing Utilization in Modern Warehouse Scale Computers via Sensible Co-locations

Managing Performance Interference Effects for QoS-Aware Clouds

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

Data Vortex Users Contemplate the Future of Supercomputing

October 19, 2017

Last month (Sept. 11-12), HPC networking company Data Vortex held its inaugural users group at Pacific Northwest National Laboratory (PNNL) bringing together about 30 participants from industry, government and academia t Read more…

By Tiffany Trader

AI Self-Training Goes Forward at Google DeepMind

October 19, 2017

DeepMind, Google’s AI research organization, announced today in a blog that AlphaGo Zero, the latest evolution of AlphaGo (the first computer program to defeat a Go world champion) trained itself within three days to play Go at a superhuman level (i.e., better than any human) – and to beat the old version of AlphaGo – without leveraging human expertise, data or training. Read more…

By Doug Black

Researchers Scale COSMO Climate Code to 4888 GPUs on Piz Daint

October 17, 2017

Effective global climate simulation, sorely needed to anticipate and cope with global warming, has long been computationally challenging. Two of the major obstacles are the needed resolution and prolonged time to compute Read more…

By John Russell

HPE Extreme Performance Solutions

Transforming Genomic Analytics with HPC-Accelerated Insights

Advancements in the field of genomics are revolutionizing our understanding of human biology, rapidly accelerating the discovery and treatment of genetic diseases, and dramatically improving human health. Read more…

Student Cluster Competition Coverage New Home

October 16, 2017

Hello computer sports fans! This is the first of many (many!) articles covering the world-wide phenomenon of Student Cluster Competitions. Finally, the Student Cluster Competition coverage has come to its natural home: H Read more…

By Dan Olds

Data Vortex Users Contemplate the Future of Supercomputing

October 19, 2017

Last month (Sept. 11-12), HPC networking company Data Vortex held its inaugural users group at Pacific Northwest National Laboratory (PNNL) bringing together ab Read more…

By Tiffany Trader

AI Self-Training Goes Forward at Google DeepMind

October 19, 2017

DeepMind, Google’s AI research organization, announced today in a blog that AlphaGo Zero, the latest evolution of AlphaGo (the first computer program to defeat a Go world champion) trained itself within three days to play Go at a superhuman level (i.e., better than any human) – and to beat the old version of AlphaGo – without leveraging human expertise, data or training. Read more…

By Doug Black

Student Cluster Competition Coverage New Home

October 16, 2017

Hello computer sports fans! This is the first of many (many!) articles covering the world-wide phenomenon of Student Cluster Competitions. Finally, the Student Read more…

By Dan Olds

Intel Delivers 17-Qubit Quantum Chip to European Research Partner

October 10, 2017

On Tuesday, Intel delivered a 17-qubit superconducting test chip to research partner QuTech, the quantum research institute of Delft University of Technology (TU Delft) in the Netherlands. The announcement marks a major milestone in the 10-year, $50-million collaborative relationship with TU Delft and TNO, the Dutch Organization for Applied Research, to accelerate advancements in quantum computing. Read more…

By Tiffany Trader

Fujitsu Tapped to Build 37-Petaflops ABCI System for AIST

October 10, 2017

Fujitsu announced today it will build the long-planned AI Bridging Cloud Infrastructure (ABCI) which is set to become the fastest supercomputer system in Japan Read more…

By John Russell

HPC Chips – A Veritable Smorgasbord?

October 10, 2017

For the first time since AMD's ill-fated launch of Bulldozer the answer to the question, 'Which CPU will be in my next HPC system?' doesn't have to be 'Whichever variety of Intel Xeon E5 they are selling when we procure'. Read more…

By Dairsie Latimer

Delays, Smoke, Records & Markets – A Candid Conversation with Cray CEO Peter Ungaro

October 5, 2017

Earlier this month, Tom Tabor, publisher of HPCwire and I had a very personal conversation with Cray CEO Peter Ungaro. Cray has been on something of a Cinderell Read more…

By Tiffany Trader & Tom Tabor

Intel Debuts Programmable Acceleration Card

October 5, 2017

With a view toward supporting complex, data-intensive applications, such as AI inference, video streaming analytics, database acceleration and genomics, Intel i Read more…

By Doug Black

Reinders: “AVX-512 May Be a Hidden Gem” in Intel Xeon Scalable Processors

June 29, 2017

Imagine if we could use vector processing on something other than just floating point problems.  Today, GPUs and CPUs work tirelessly to accelerate algorithms Read more…

By James Reinders

NERSC Scales Scientific Deep Learning to 15 Petaflops

August 28, 2017

A collaborative effort between Intel, NERSC and Stanford has delivered the first 15-petaflops deep learning software running on HPC platforms and is, according Read more…

By Rob Farber

Oracle Layoffs Reportedly Hit SPARC and Solaris Hard

September 7, 2017

Oracle’s latest layoffs have many wondering if this is the end of the line for the SPARC processor and Solaris OS development. As reported by multiple sources Read more…

By John Russell

US Coalesces Plans for First Exascale Supercomputer: Aurora in 2021

September 27, 2017

At the Advanced Scientific Computing Advisory Committee (ASCAC) meeting, in Arlington, Va., yesterday (Sept. 26), it was revealed that the "Aurora" supercompute Read more…

By Tiffany Trader

How ‘Knights Mill’ Gets Its Deep Learning Flops

June 22, 2017

Intel, the subject of much speculation regarding the delayed, rewritten or potentially canceled “Aurora” contract (the Argonne Lab part of the CORAL “ Read more…

By Tiffany Trader

Google Releases Deeplearn.js to Further Democratize Machine Learning

August 17, 2017

Spreading the use of machine learning tools is one of the goals of Google’s PAIR (People + AI Research) initiative, which was introduced in early July. Last w Read more…

By John Russell

GlobalFoundries Puts Wind in AMD’s Sails with 12nm FinFET

September 24, 2017

From its annual tech conference last week (Sept. 20), where GlobalFoundries welcomed more than 600 semiconductor professionals (reaching the Santa Clara venue Read more…

By Tiffany Trader

Nvidia Responds to Google TPU Benchmarking

April 10, 2017

Nvidia highlights strengths of its newest GPU silicon in response to Google's report on the performance and energy advantages of its custom tensor processor. Read more…

By Tiffany Trader

Leading Solution Providers

Graphcore Readies Launch of 16nm Colossus-IPU Chip

July 20, 2017

A second $30 million funding round for U.K. AI chip developer Graphcore sets up the company to go to market with its “intelligent processing unit” (IPU) in Read more…

By Tiffany Trader

Amazon Debuts New AMD-based GPU Instances for Graphics Acceleration

September 12, 2017

Last week Amazon Web Services (AWS) streaming service, AppStream 2.0, introduced a new GPU instance called Graphics Design intended to accelerate graphics. The Read more…

By John Russell

EU Funds 20 Million Euro ARM+FPGA Exascale Project

September 7, 2017

At the Barcelona Supercomputer Centre on Wednesday (Sept. 6), 16 partners gathered to launch the EuroEXA project, which invests €20 million over three-and-a-half years into exascale-focused research and development. Led by the Horizon 2020 program, EuroEXA picks up the banner of a triad of partner projects — ExaNeSt, EcoScale and ExaNoDe — building on their work... Read more…

By Tiffany Trader

Delays, Smoke, Records & Markets – A Candid Conversation with Cray CEO Peter Ungaro

October 5, 2017

Earlier this month, Tom Tabor, publisher of HPCwire and I had a very personal conversation with Cray CEO Peter Ungaro. Cray has been on something of a Cinderell Read more…

By Tiffany Trader & Tom Tabor

Cray Moves to Acquire the Seagate ClusterStor Line

July 28, 2017

This week Cray announced that it is picking up Seagate's ClusterStor HPC storage array business for an undisclosed sum. "In short we're effectively transitioning the bulk of the ClusterStor product line to Cray," said CEO Peter Ungaro. Read more…

By Tiffany Trader

Intel Launches Software Tools to Ease FPGA Programming

September 5, 2017

Field Programmable Gate Arrays (FPGAs) have a reputation for being difficult to program, requiring expertise in specialty languages, like Verilog or VHDL. Easin Read more…

By Tiffany Trader

IBM Advances Web-based Quantum Programming

September 5, 2017

IBM Research is pairing its Jupyter-based Data Science Experience notebook environment with its cloud-based quantum computer, IBM Q, in hopes of encouraging a new class of entrepreneurial user to solve intractable problems that even exceed the capabilities of the best AI systems. Read more…

By Alex Woodie

HPC Chips – A Veritable Smorgasbord?

October 10, 2017

For the first time since AMD's ill-fated launch of Bulldozer the answer to the question, 'Which CPU will be in my next HPC system?' doesn't have to be 'Whichever variety of Intel Xeon E5 they are selling when we procure'. Read more…

By Dairsie Latimer

  • arrow
  • Click Here for More Headlines
  • arrow
Share This