SC13 Research Highlight: There Goes the Performance Neighborhood…

By Drs. Abhinav Bhatele, Kathryn Mohror, Steven Langer & Katherine Isaacs

November 16, 2013

Message passing can take up a significant fraction of the run time for massively parallel science simulation codes. Consistently high message passing rates are required for these codes to deliver good performance. At Supercomputing 2013 (SC13), our research team from Lawrence Livermore (LLNL) will present the results of our study that show that run-to-run variability in message passing rates can reduce throughput by 30% or more due to contention with other jobs for the network links.

Performance variability can result in individual jobs running slower, which in turn can lead to a longer wait for the science results and increase the waiting time in the queue for other jobs.  Reducing such variability could improve overall throughput at a computer center and save energy costs.  Performance variability also impacts the development cycle for high-performance computing (HPC) applications. It can complicate tasks such as: debugging performance issues in an application code, quantifying the effects of code changes on performance, measuring the effects of compiler or system software changes, and determining how much time to request for a batch job. Thus, we set out to investigate the possible sources of such performance variability on supercomputer systems.

In our study, we focused on pF3D, a code that simulates laser-plasma interactions in experiments at the National Ignition Facility at LLNL.  In 2011, we began doing production runs of pF3D on Cielo, a 1.37 Petaflop/s Cray XE6 system installed at Los Alamos. Concurrently, we ran pF3D on Dawn, an IBM Blue Gene/P system at LLNL. The run times of identical jobs on Cielo varied by 20% while there was very little variability on Dawn. The differences in run time were due to varying message passing rates. These early results prompted us to do a systematic study of message rate variability on three U.S.  Department of Energy (DOE) supercomputers: Intrepid, an IBM Blue Gene/P at Argonne (ANL), Mira, an IBM Blue Gene/Q at Argonne, and Hopper, a Cray XE6 at Lawrence Berkeley (LBNL).

Over the course of forty-five days, we submitted a short benchmarking run of pF3D every day to record the performance behavior of the application and some information about the system state, including the shape of the job partition allocated to the job, and other jobs running on the system and their node allocations. The “shape” of the job partition refers to the physical locations of the allocated nodes in the interconnect topology of the system.  Mira has a five-dimensional torus interconnect while Hopper and Intrepid have a three-dimensional torus interconnect. Below, we show a plot of the average messaging rate for each job as a function of when it was run on the three systems.  We compute the average messaging rate by dividing the total volume of communication in bytes by the total time spent in sending the messages over the network.


Click to enlarge

We see that on the IBM systems, Intrepid and Mira, there is negligible variation in the messaging performance. However, on the Cray system (Hopper), the slowest job on any given day may run at half the speed of the fastest job. Application users choose the amount of work to assign to each batch job to ensure that there is sufficient time to save results even on a day with poor performance.  This results in less average work completed per batch job than on a system with repeatable performance and the need for more batch job slots (and more calendar days) to complete a simulation.

In this SC13 paper (presentation schedule below), we attempt to narrow down the root causes of this performance variability on Hopper.  Several factors can make the performance of an application variable within and across batch jobs. These factors include noise from operating system (OS) daemons, communication variability arising from the shape of the allocated partition, and interference from other jobs sharing the same network links.  Below, we present observational evidence that indicates which factor leads to the highest performance variability. We show the placement of pF3D (blue) and conflicting jobs (other colors) on Hopper for two separate short runs in the figure below. The job from April 11 (left) yielded a messaging rate nearly 25% below that of the job run on April 16 (right). The two jobs had the same node placement, but the slower April 11 job was surrounded by several other jobs, including a large communication-heavy job (green).  More detailed analysis that provides stronger evidence for the effect of inter-job interference on performance can be found in the paper.


Acknowledgement: This work was performed under the auspices of the U.S. Department of Energy by Lawrence Livermore National Laboratory under Contract DE-AC52-07NA27344. This work was funded by the Laboratory Directed Research and Development Program at LLNL under project tracking codes 13-ERD-055 and 13-FS-002 (LLNL-MI-645823).

Read more about this research at

Presentation Schedule:

Authors: Abhinav Bhatele, Kathryn Mohror, Steven H. Langer, Katherine E. Isaacs

Day: Tuesday (November 19, 2013)

Time: 4:00 – 4:30 PM

Location: 401/402/403

About the Authors

bhateleDr. Abhinav Bhatele is a computer scientist in the Center for Applied Scientific Computing at Lawrence Livermore National Laboratory. His interests lie in performance optimizations through analysis, visualization and tuning and developing algorithms for high-end parallel systems.


mahKathryn Mohror is a computer scientist at Lawrence Livermore National Laboratory (LLNL). She is a member of the Scalability Team at LLNL and her research on high-end computing systems is currently focused on scalable fault tolerant computing and performance measurement and analysis.
Steven Langer is currently a computational physicist at Lawrence Livermore National Laboratory. His research interests include inertial confinement fusion, performance analysis of HPC applications, scalability of message passing and I/O in applications, and understanding how to modify multi-physics simulation codes to run efficiently on upcoming exascale hardware.
Katherine Isaacs is a graduate student at the University of California, Davis. Her research focuses on information visualization techniques for performance analysis.
Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

Geospatial Data Research Leverages GPUs

August 17, 2017

MapD Technologies, the GPU-accelerated database specialist, said it is working with university researchers on leveraging graphics processors to advance geospatial analytics. The San Francisco-based company is collabor Read more…

By George Leopold

Intel, NERSC and University Partners Launch New Big Data Center

August 17, 2017

A collaboration between the Department of Energy’s National Energy Research Scientific Computing Center (NERSC), Intel and five Intel Parallel Computing Centers (IPCCs) has resulted in a new Big Data Center (BDC) that Read more…

By Linda Barney

Google Releases Deeplearn.js to Further Democratize Machine Learning

August 17, 2017

Spreading the use of machine learning tools is one of the goals of Google’s PAIR (People + AI Research) initiative, which was introduced in early July. Last week the cloud giant released deeplearn.js as part of that in Read more…

By John Russell

HPE Extreme Performance Solutions

Leveraging Deep Learning for Fraud Detection

Advancements in computing technologies and the expanding use of e-commerce platforms have dramatically increased the risk of fraud for financial services companies and their customers. Read more…

Spoiler Alert: Glimpse Next Week’s Solar Eclipse Via Simulation from TACC, SDSC, and NASA

August 17, 2017

Can’t wait to see next week’s solar eclipse? You can at least catch glimpses of what scientists expect it will look like. A team from Predictive Science Inc. (PSI), based in San Diego, working with Stampede2 at the Read more…

By John Russell

Microsoft Bolsters Azure With Cloud HPC Deal

August 15, 2017

Microsoft has acquired cloud computing software vendor Cycle Computing in a move designed to bring orchestration tools along with high-end computing access capabilities to the cloud. Terms of the acquisition were not disclosed. Read more…

By George Leopold

HPE Ships Supercomputer to Space Station, Final Destination Mars

August 14, 2017

With a manned mission to Mars on the horizon, the demand for space-based supercomputing is at hand. Today HPE and NASA sent the first off-the-shelf HPC system i Read more…

By Tiffany Trader

AMD EPYC Video Takes Aim at Intel’s Broadwell

August 14, 2017

Let the benchmarking begin. Last week, AMD posted a YouTube video in which one of its EPYC-based systems outperformed a ‘comparable’ Intel Broadwell-based s Read more…

By John Russell

Deep Learning Thrives in Cancer Moonshot

August 8, 2017

The U.S. War on Cancer, certainly a worthy cause, is a collection of programs stretching back more than 40 years and abiding under many banners. The latest is t Read more…

By John Russell

IBM Raises the Bar for Distributed Deep Learning

August 8, 2017

IBM is announcing today an enhancement to its PowerAI software platform aimed at facilitating the practical scaling of AI models on today’s fastest GPUs. Scal Read more…

By Tiffany Trader

IBM Storage Breakthrough Paves Way for 330TB Tape Cartridges

August 3, 2017

IBM announced yesterday a new record for magnetic tape storage that it says will keep tape storage density on a Moore's law-like path far into the next decade. Read more…

By Tiffany Trader

AMD Stuffs a Petaflops of Machine Intelligence into 20-Node Rack

August 1, 2017

With its Radeon “Vega” Instinct datacenter GPUs and EPYC “Naples” server chips entering the market this summer, AMD has positioned itself for a two-head Read more…

By Tiffany Trader

Cray Moves to Acquire the Seagate ClusterStor Line

July 28, 2017

This week Cray announced that it is picking up Seagate's ClusterStor HPC storage array business for an undisclosed sum. "In short we're effectively transitioning the bulk of the ClusterStor product line to Cray," said CEO Peter Ungaro. Read more…

By Tiffany Trader

How ‘Knights Mill’ Gets Its Deep Learning Flops

June 22, 2017

Intel, the subject of much speculation regarding the delayed, rewritten or potentially canceled “Aurora” contract (the Argonne Lab part of the CORAL “ Read more…

By Tiffany Trader

Nvidia’s Mammoth Volta GPU Aims High for AI, HPC

May 10, 2017

At Nvidia's GPU Technology Conference (GTC17) in San Jose, Calif., this morning, CEO Jensen Huang announced the company's much-anticipated Volta architecture a Read more…

By Tiffany Trader

Reinders: “AVX-512 May Be a Hidden Gem” in Intel Xeon Scalable Processors

June 29, 2017

Imagine if we could use vector processing on something other than just floating point problems.  Today, GPUs and CPUs work tirelessly to accelerate algorithms Read more…

By James Reinders

Quantum Bits: D-Wave and VW; Google Quantum Lab; IBM Expands Access

March 21, 2017

For a technology that’s usually characterized as far off and in a distant galaxy, quantum computing has been steadily picking up steam. Just how close real-wo Read more…

By John Russell

Russian Researchers Claim First Quantum-Safe Blockchain

May 25, 2017

The Russian Quantum Center today announced it has overcome the threat of quantum cryptography by creating the first quantum-safe blockchain, securing cryptocurrencies like Bitcoin, along with classified government communications and other sensitive digital transfers. Read more…

By Doug Black

Nvidia Responds to Google TPU Benchmarking

April 10, 2017

Nvidia highlights strengths of its newest GPU silicon in response to Google's report on the performance and energy advantages of its custom tensor processor. Read more…

By Tiffany Trader

Groq This: New AI Chips to Give GPUs a Run for Deep Learning Money

April 24, 2017

CPUs and GPUs, move over. Thanks to recent revelations surrounding Google’s new Tensor Processing Unit (TPU), the computing world appears to be on the cusp of Read more…

By Alex Woodie

HPC Compiler Company PathScale Seeks Life Raft

March 23, 2017

HPCwire has learned that HPC compiler company PathScale has fallen on difficult times and is asking the community for help or actively seeking a buyer for its a Read more…

By Tiffany Trader

Leading Solution Providers

Trump Budget Targets NIH, DOE, and EPA; No Mention of NSF

March 16, 2017

President Trump’s proposed U.S. fiscal 2018 budget issued today sharply cuts science spending while bolstering military spending as he promised during the cam Read more…

By John Russell

CPU-based Visualization Positions for Exascale Supercomputing

March 16, 2017

In this contributed perspective piece, Intel’s Jim Jeffers makes the case that CPU-based visualization is now widely adopted and as such is no longer a contrarian view, but is rather an exascale requirement. Read more…

By Jim Jeffers, Principal Engineer and Engineering Leader, Intel

Google Debuts TPU v2 and will Add to Google Cloud

May 25, 2017

Not long after stirring attention in the deep learning/AI community by revealing the details of its Tensor Processing Unit (TPU), Google last week announced the Read more…

By John Russell

Six Exascale PathForward Vendors Selected; DoE Providing $258M

June 15, 2017

The much-anticipated PathForward awards for hardware R&D in support of the Exascale Computing Project were announced today with six vendors selected – AMD Read more…

By John Russell

Top500 Results: Latest List Trends and What’s in Store

June 19, 2017

Greetings from Frankfurt and the 2017 International Supercomputing Conference where the latest Top500 list has just been revealed. Although there were no major Read more…

By Tiffany Trader

IBM Clears Path to 5nm with Silicon Nanosheets

June 5, 2017

Two years since announcing the industry’s first 7nm node test chip, IBM and its research alliance partners GlobalFoundries and Samsung have developed a proces Read more…

By Tiffany Trader

Messina Update: The US Path to Exascale in 16 Slides

April 26, 2017

Paul Messina, director of the U.S. Exascale Computing Project, provided a wide-ranging review of ECP’s evolving plans last week at the HPC User Forum. Read more…

By John Russell

Graphcore Readies Launch of 16nm Colossus-IPU Chip

July 20, 2017

A second $30 million funding round for U.K. AI chip developer Graphcore sets up the company to go to market with its “intelligent processing unit” (IPU) in Read more…

By Tiffany Trader

  • arrow
  • Click Here for More Headlines
  • arrow
Share This