Intel Sheds Light on the ‘Corner to Landing’ Leap

By Nicole Hemsoth

December 6, 2013

Since the first details about the MIC architecture emerged, Intel has continually harkened back to their vision of offering a high degree of parallelism inside a power efficient package that could promise programmability.

With the eventual entry of the next generation Xeon Phi hitting the market in years to come with its (still unstated) high number of cores, on-package memory, ability to shape shift from coprocessor to processor along the x86 continuum, many are wondering about what kind of programmatic muscle will be needed to spring from Knights Corner to Knights Landing.

In essence, as we have touched on already, one can look at Knights Landing as simply a new Xeon with higher core counts since at least some of the complexities of using it as a coprocessor will no longer be an issue. Unlike with the current Xeon Phi, transfers across PCIe are eliminated, memory is local and Landing acts as a true processor that can carry over the benefits of parallelism and efficiency of Phi in a processor form factor while still offering the option to use it as a coprocessor for specific highly parallel parts of a given workload. So this should make programming for one of these essentially the same as programming for Xeon—that is, in theory.

Despite the emphasis on extending programmability, make no mistake, it’s not as though parallel programming is suddenly going to become magically simple–and certainly that’s still not the case for using coprocessors, says James Reinders, Intel’s software director. However, there are some notable features that will make the transition more seamless.

When it comes to using Knights Landing as a coprocessor, the real benefits between Knights Corner and Landing will become more apparent. As it stands now, many programmers using accelerators or coprocessor use offload models on mixed (serial and highly parallel) code where they write their programs to run on the processor but with certain highly parallel bits offloaded. The advantage there is that there’s the power of the processors, which compared to accelerators/Phi are much better at serial tasks. Of course, programmers are keenly aware of Amdahl’s Law and are looking to OpenACC and OpenMP directives to address some of these problems with offloading—problems that Intel is addressing by nixing the offloading middleman.

As Reinders described, “One of the big things about Knight’s Landing in this regard is that to make it a processor we had to reduce the effects of Amdhal’s Law. Making Knights Landing a processor means we wanted to build a system around it where the program runs on it but it “offloads itself” in a sense—there’s no such thing as offloading to yourself; you just switch between being somewhat serial to highly parallel just like you do in a program you write for a processor today. However, Knights Landing is more capable of handling highly parallel workloads than any other processor today.”

The other way to program for Knights Landing (or its predecessor, for that matter) is to just treat it as a processor hooked together with other Xeons or Phis using MPI. Landing will support that model as both a processor or coprocessor, Reinders said. “A lot of users today are just taking their applications and using MPI instead of offloading. When you build a Knight’s Landing machine they can all run MPI and since they run a full OS you can do anything that a processor would do.”

By the way, as a side note on the OS, many users on the HPC front will likely not let the OS run wild and eat up a number of the cores (and there are definitely more than 61 on the new chips) and will also have to prevent the OS from munching into the high bandwidth memory it sees sitting nearby. It’s a matter of user-set policy for the number of cores the OS runs on and as for keeping the OS’s greedy hands off the new memory on board, there are workarounds in development around that.

With that specific OS piece in mind, however, it’s easy to see why Reinders is giddy about Landing. “You can think of Knights Landing exactly like it’s a Xeon with lots and lots of (but-we-still-can’t-tell-you-how-many) cores. The big difference is how good it is at highly parallel workloads. It’s a high core count Xeon. That’s how we get extreme compatibility with Knights Landing to make it a processor—every OS that boots on it will look at think it’s a just a Xeon on steroids; it shouldn’t look any different. But again you can set in policy to run it on one of the cores.” He expects that OEMs that supply systems will continue to keep configuring machines with these policies that favor keeping the OS contained and letting the applications have full reign on the other cores.

“We will have a few more years under our belts before we launch Knights Landing and we’ll use that time to continue to refine our hardware and software,”Reinders continues. “But overall, Knights Landing offers a very straightforward migration from Knights Corner, so anyone using the first generation Xeon Phi can move very easily—the thing that is most exciting is that it gets us closer to our vision of programmability.”

Among some of those refinements that will be present in Knights Landing are the 512-bit SIMD capabilities, which will eventually be extended across the entire Intel processor line. Currently with AVX2 and its 256 bit width users can pull 4 double precision operations (or 8 singles) from a single clock, but with the introduction of 512-bit, that performance will double for both single and double-precision. There is already 512 capability built into current Xeon Phi, but it’s only for use in the coprocessor since it hasn’t been fully synched with the full set of x86 capabilities. People using the current Phi thus don’t have the throughput possibilities or all the functionality that Intel will roll out with Knights Landing.

Reinders has been teaching users how to tap into Xeon Phi and as he’s introducing concepts leading up to Knights Landing. Everyone is “looking for holes in the armor,” but he argues that the ones they know about they’re working to address through the ecosystem, compilers, and in house. “The simple answer is that anyone who already programs for Knights Corner will find the Landing leap an easy one since there’s no new learning,” he says.

This bodes well for Intel to take this highly parallel approach well beyond HPC applications in the future, especially if they continue to push the idea that there’s nothing “special” (i.e., difficult or accelerator-like for programmers) about it—that it’s simply a high core count processor. The beauty is that they can eventually round out their suite of processor choices so users can continually tailor these choices around their workloads and the degree of parallelism, performance and power required.

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

Exascale Computing Project Names Doug Kothe as Director

September 20, 2017

The Department of Energy’s Exascale Computing Project (ECP) has named Doug Kothe as its new director effective October 1. He replaces Paul Messina, who is stepping down after two years to return to Argonne National L Read more…

Takeaways from the Milwaukee HPC User Forum

September 19, 2017

Milwaukee’s elegant Pfister Hotel hosted approximately 100 attendees for the 66th HPC User Forum (September 5-7, 2017). In the original home city of Pabst Blue Ribbon and Harley Davidson motorcycles the agenda addresse Read more…

By Merle Giles

NSF Awards $10M to Extend Chameleon Cloud Testbed Project

September 19, 2017

The National Science Foundation has awarded a second phase, $10 million grant to the Chameleon cloud computing testbed project led by University of Chicago with partners at the Texas Advanced Computing Center (TACC), Ren Read more…

By John Russell

HPE Extreme Performance Solutions

HPE Prepares Customers for Success with the HPC Software Portfolio

High performance computing (HPC) software is key to harnessing the full power of HPC environments. Development and management tools enable IT departments to streamline installation and maintenance of their systems as well as create, optimize, and run their HPC applications. Read more…

NERSC Simulations Shed Light on Fusion Reaction Turbulence

September 19, 2017

Understanding fusion reactions in detail – particularly plasma turbulence – is critical to the effort to bring fusion power to reality. Recent work including roughly 70 million hours of compute time at the National E Read more…

Exascale Computing Project Names Doug Kothe as Director

September 20, 2017

The Department of Energy’s Exascale Computing Project (ECP) has named Doug Kothe as its new director effective October 1. He replaces Paul Messina, who is s Read more…

Takeaways from the Milwaukee HPC User Forum

September 19, 2017

Milwaukee’s elegant Pfister Hotel hosted approximately 100 attendees for the 66th HPC User Forum (September 5-7, 2017). In the original home city of Pabst Blu Read more…

By Merle Giles

Kathy Yelick Charts the Promise and Progress of Exascale Science

September 15, 2017

On Friday, Sept. 8, Kathy Yelick of Lawrence Berkeley National Laboratory and the University of California, Berkeley, delivered the keynote address on “Breakt Read more…

By Tiffany Trader

DARPA Pledges Another $300 Million for Post-Moore’s Readiness

September 14, 2017

The Defense Advanced Research Projects Agency (DARPA) launched a giant funding effort to ensure the United States can sustain the pace of electronic innovation vital to both a flourishing economy and a secure military. Under the banner of the Electronics Resurgence Initiative (ERI), some $500-$800 million will be invested in post-Moore’s Law technologies. Read more…

By Tiffany Trader

IBM Breaks Ground for Complex Quantum Chemistry

September 14, 2017

IBM has reported the use of a novel algorithm to simulate BeH2 (beryllium-hydride) on a quantum computer. This is the largest molecule so far simulated on a quantum computer. The technique, which used six qubits of a seven-qubit system, is an important step forward and may suggest an approach to simulating ever larger molecules. Read more…

By John Russell

Cubes, Culture, and a New Challenge: Trish Damkroger Talks about Life at Intel—and Why HPC Matters More Than Ever

September 13, 2017

Trish Damkroger wasn’t looking to change jobs when she attended SC15 in Austin, Texas. Capping a 15-year career within Department of Energy (DOE) laboratories, she was acting Associate Director for Computation at Lawrence Livermore National Laboratory (LLNL). Her mission was to equip the lab’s scientists and research partners with resources that would advance their cutting-edge work... Read more…

By Jan Rowell

EU Funds 20 Million Euro ARM+FPGA Exascale Project

September 7, 2017

At the Barcelona Supercomputer Centre on Wednesday (Sept. 6), 16 partners gathered to launch the EuroEXA project, which invests €20 million over three-and-a-half years into exascale-focused research and development. Led by the Horizon 2020 program, EuroEXA picks up the banner of a triad of partner projects — ExaNeSt, EcoScale and ExaNoDe — building on their work... Read more…

By Tiffany Trader

MIT-IBM Watson AI Lab Targets Algorithms, AI Physics

September 7, 2017

Investment continues to flow into artificial intelligence research, especially in key areas such as AI algorithms that promise to move the technology from speci Read more…

By George Leopold

How ‘Knights Mill’ Gets Its Deep Learning Flops

June 22, 2017

Intel, the subject of much speculation regarding the delayed, rewritten or potentially canceled “Aurora” contract (the Argonne Lab part of the CORAL “ Read more…

By Tiffany Trader

Reinders: “AVX-512 May Be a Hidden Gem” in Intel Xeon Scalable Processors

June 29, 2017

Imagine if we could use vector processing on something other than just floating point problems.  Today, GPUs and CPUs work tirelessly to accelerate algorithms Read more…

By James Reinders

NERSC Scales Scientific Deep Learning to 15 Petaflops

August 28, 2017

A collaborative effort between Intel, NERSC and Stanford has delivered the first 15-petaflops deep learning software running on HPC platforms and is, according Read more…

By Rob Farber

Russian Researchers Claim First Quantum-Safe Blockchain

May 25, 2017

The Russian Quantum Center today announced it has overcome the threat of quantum cryptography by creating the first quantum-safe blockchain, securing cryptocurrencies like Bitcoin, along with classified government communications and other sensitive digital transfers. Read more…

By Doug Black

Oracle Layoffs Reportedly Hit SPARC and Solaris Hard

September 7, 2017

Oracle’s latest layoffs have many wondering if this is the end of the line for the SPARC processor and Solaris OS development. As reported by multiple sources Read more…

By John Russell

Google Debuts TPU v2 and will Add to Google Cloud

May 25, 2017

Not long after stirring attention in the deep learning/AI community by revealing the details of its Tensor Processing Unit (TPU), Google last week announced the Read more…

By John Russell

Six Exascale PathForward Vendors Selected; DoE Providing $258M

June 15, 2017

The much-anticipated PathForward awards for hardware R&D in support of the Exascale Computing Project were announced today with six vendors selected – AMD Read more…

By John Russell

Top500 Results: Latest List Trends and What’s in Store

June 19, 2017

Greetings from Frankfurt and the 2017 International Supercomputing Conference where the latest Top500 list has just been revealed. Although there were no major Read more…

By Tiffany Trader

Leading Solution Providers

IBM Clears Path to 5nm with Silicon Nanosheets

June 5, 2017

Two years since announcing the industry’s first 7nm node test chip, IBM and its research alliance partners GlobalFoundries and Samsung have developed a proces Read more…

By Tiffany Trader

Nvidia Responds to Google TPU Benchmarking

April 10, 2017

Nvidia highlights strengths of its newest GPU silicon in response to Google's report on the performance and energy advantages of its custom tensor processor. Read more…

By Tiffany Trader

Graphcore Readies Launch of 16nm Colossus-IPU Chip

July 20, 2017

A second $30 million funding round for U.K. AI chip developer Graphcore sets up the company to go to market with its “intelligent processing unit” (IPU) in Read more…

By Tiffany Trader

Google Releases Deeplearn.js to Further Democratize Machine Learning

August 17, 2017

Spreading the use of machine learning tools is one of the goals of Google’s PAIR (People + AI Research) initiative, which was introduced in early July. Last w Read more…

By John Russell

EU Funds 20 Million Euro ARM+FPGA Exascale Project

September 7, 2017

At the Barcelona Supercomputer Centre on Wednesday (Sept. 6), 16 partners gathered to launch the EuroEXA project, which invests €20 million over three-and-a-half years into exascale-focused research and development. Led by the Horizon 2020 program, EuroEXA picks up the banner of a triad of partner projects — ExaNeSt, EcoScale and ExaNoDe — building on their work... Read more…

By Tiffany Trader

Amazon Debuts New AMD-based GPU Instances for Graphics Acceleration

September 12, 2017

Last week Amazon Web Services (AWS) streaming service, AppStream 2.0, introduced a new GPU instance called Graphics Design intended to accelerate graphics. The Read more…

By John Russell

Cray Moves to Acquire the Seagate ClusterStor Line

July 28, 2017

This week Cray announced that it is picking up Seagate's ClusterStor HPC storage array business for an undisclosed sum. "In short we're effectively transitioning the bulk of the ClusterStor product line to Cray," said CEO Peter Ungaro. Read more…

By Tiffany Trader

IBM Advances Web-based Quantum Programming

September 5, 2017

IBM Research is pairing its Jupyter-based Data Science Experience notebook environment with its cloud-based quantum computer, IBM Q, in hopes of encouraging a new class of entrepreneurial user to solve intractable problems that even exceed the capabilities of the best AI systems. Read more…

By Alex Woodie

  • arrow
  • Click Here for More Headlines
  • arrow
Share This