Tackling the Power and Energy Wall for Future HPC Systems

By Performance and Architecture Lab (PAL) at PNNL

December 17, 2013

A Perspective from the Paci fic Northwest National Laboratory*

As the cost of powering a supercomputer or a datacenter increases, next generation exascale systems need to be considerably more power- and energy-efficient than current supercomputers to be of practical use. Constrained power consumption (20-25MW for the entire system is the target that the DOE Office of Science gave to the HPC community) is one of the limiting factors on the road to achieve sustainable performance at exascale. In fact, the power challenge is so fundamental that other challenges can be reduced to power limitations. For example, operating at near-threshold voltage (NTV) in order to perform computation within a given power budget may considerably increase the soft-error rate (resilience challenge). Unlike petascale systems, where the primary concern was performance, exascale systems need to climb the power and energy walls in order to deliver sustainable exaflops performance. At the Pacifi c Northwest Laboratory (PNNL) we are exploring holistically energy and power efficiency aspects at all levels of granularity, from processor architecture to system integration. We are also tackling the power and energy problems from several angles, from system software and programming models to performance and power modeling of scientifi c applications and extreme scale systems.

PNNL Research Areas Fig1

PNNL’s computing facilities, such as its Institutional HPC system (PIC), and an earlier testbed, the Energy Smart Data Center (ESDC), provide research platforms to address what-if questions related to the use of suitable datacenter metrics that are meaningful to the HPC community. The measurement harness of the ESDC entailed over thousand out-of-band sensors comprising power, flow, pressure and temperature at the machine room and at the IT equipment. PIC is another example that substantiates our integrated datacenter vision to drive energy efficiency research. This system is housed in a geothermally cooled datacenter with rear-door heat exchangers. The facility is instrumented at the machine room and system level, providing insight into macro-level machine room power efficiencies and micro-level energy efficiencies at the server and mother-board component levels.

Despite its importance for future exascale systems, power is still not considered a first-class citizen, which complicates the development of power-aware software algorithms. In PNNL’s vision, power should be considered a resource, just as processing elements or memory modules, and should be managed as such by the system software. System software must be able to precisely measure (in-band) power resource utilization, i.e., how much power is consumed by each system component at any given time. More importantly, the system software should adapt the application to the contingent execution environment, e.g, by allocating sustained power to threads on the application’s critical path or promptly moving idle cores to low-power states. The design and development of such self-aware/self-adaptive system software is an active research area at PNNL. We recently analyzed the power characteristics of scientifi c applications from the DOE ASCR’s Exascale Co-Design Center and, in general, in the HPC community to identify opportunities for power savings. Given the lack of in-band, fine-grained (both in space and time) power sensors, we develop an accurate per-core proxy power sensor model that estimates the active power of each core by inspecting the cores’ activity. We use statistical regression techniques to formulate closed-form expressions for the estimated core and system power consumption. These techniques enable us to develop power-aware algorithms and characterize applications running even on non-instrumented compute nodes. Our experiments show that processes in the same application may not have the same power profi le and/or may alternate high-power with low-power phases independently from one another. These alternating behaviors raise opportunities for shifting power towards computing-demanding processes, hereby saving power without diminishing performance.

There is a strong agreement among researchers on the increasing cost of data movement with respect to computation. This ratio will further increase in future systems that will approach NTV operation levels: the energy consumption of a double precision register-to-register floating point operation is expected to decrease by 10x by 2018. The energy cost of moving data from memory to processor is not expected to follow the same trend, hence the relative energy cost of data movement with respect to performing a register-to-register operation will increase (energy wall — analogous to the memory wall). In a recent study we modeled the energy cost of moving data across the memory hierarchy of current systems and analyzed the energy cost of data movement for scientifi c applications. In this study, we answer several important questions such as what is the amount of energy spent in data movement with respect to the total energy consumption of an application or what is the dominant component of data movement energy for current and future parallel applications. Our results show that the energy cost of data movement impact di fferently on each application, ranging from 18% to 40%. This percentage might increase in the future, as the energy cost of performing computation decreases. To avoid such scenario, new technologies, such as Processing-In- Memory, Non-Volatile RAM and 3D-stacked memory, become essential for the development of sustainable exascale computing. We also noticed that the energy spent in resolving data dependency, speculation and out-of-order scheduling of instructions accounts for a considerable part of the total dynamic energy, between 22% and 35%. This cost can be reduced with simpler processor core designs that are more energy efficient.

Given the increasing complexity of future exascale applications and systems, designers need new sophisticated tools to navigate the design space. These tools must capture a range of metrics that are of interest to system and application designers, including performance and power consumption. PNNL has historically developed application-specific performance tools that model the evolution of parallel applications. While these models have shown themselves to be powerful tools for understanding the mapping of applications to complex system architectures, the metrics of interest are expanding to include power consumption as well. To this end, PNNL researchers have developed a methodology for the modeling of performance and power in concert that builds upon its experience of co-designing systems and applications. This modeling capability has been developed along three axes. The first is the deployment of a workload-specific quantitative power modeling capability. Such power models accurately capture workload phases, their impact on power consumption, and how they are impacted by system architecture and con figuration (e.g., processor clock speed). The second axis is the integration of the performance and power modeling methodologies. To this end, it is critical that both modeling methods operated at the same conceptual level. In other words, application phases or components that are captured in one model must be also reflected in the other so that trade-o ffs between power and performance may be captured and quantifi ed. The last axis of development involves integrating these models with our self-aware/self-adaptive software system that will provide mechanisms for dynamically optimizing ongoing application execution. We have developed the concept of Energy Templates, which are a mechanism for passing application-specifi c behavioral information to the underlying runtime layers. Energy Templates capture per-core idle/busy states, as well as the amount of time each core expects to remain in each state, allowing runtime software to determine appropriate opportunities to exercise power saving features provided by the hardware/software platform (e.g., Dynamic Voltage and Frequency Scaling — DVFS) without negatively impacting performance. By proactively using application-speci fic information, Energy Templates are able to exploit energy savings opportunities that are not available to mechanisms that are not application-aware.

The research at PNNL is also being applied within the new DARPA program in the Power Efficiency Revolution of Embedded Technologies (PERFECT). We see that technologies being developed both for high performance computing and embedded systems are fundamentally the same. These may well converge in the future, and thus common tools and techniques can be developed that encompass both. Within PERFECT PNNL researchers are developing a coherent framework that is able to both empirically analyze current systems and predictively assess future technologies.

Finally, PNNL’s research extends to the datacenters: this research direction is approached in an integrated fashion where IT power consumption for applications of interest to the DOE is correlated with the power consumption of the supporting infrastructure. An integrated approach allows the researcher to formulate what-if questions in an HPC setting such as the applicability and efficacy of novel cooling solutions (e.g., spray cooling) at the heat source vs. a traditional global cooling solution.

Overall, PNNL is actively participating in (and in many cases leading) several DOE and DARPA projects, as well as internal projects, that aim at understanding the impact of the power and energy walls on exascale systems and deploying power- and energy-aware solutions at all levels of the system and application design and optimization. The insights gained throughout these efforts and projects will contribute towards the design of power- and energy-efficient exascale systems.

*The following PNNL researchers contributed to this piece: Adolfy Hoisie, Kevin Barker, Roberto Gioiosa, Darren J. Kerbyson, Gokcen Kestor, Joseph Manzano, Andres Marquez, Shuaiwen Song, Nathan Tallent, Antonino Tumeo, Abhinav Vishnu

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

2022 Road Trip: NASA Ames Takes Off

November 25, 2022

I left Dallas very early Friday morning after the conclusion of SC22. I had a race with the devil to get from Dallas to Mountain View, Calif., by Sunday. According to Google Maps, this 1,957 mile jaunt would be the longe Read more…

2022 Road Trip: Sandia Brain Trust Sounds Off

November 24, 2022

As the 2022 Great American Supercomputing Road Trip carries on, it’s Sandia’s turn. It was a bright sunny day when I rolled into Albuquerque after a high-speed run from Los Alamos National Laboratory. My interview su Read more…

2022 HPC Road Trip: Los Alamos

November 23, 2022

With SC22 in the rearview mirror, it’s time to get back to the 2022 Great American Supercomputing Road Trip. To refresh everyone’s memory, I jumped in the car on November 3rd and headed towards SC22 in Dallas, stoppi Read more…

Chipmakers Looking at New Architecture to Drive Computing Ahead

November 23, 2022

The ability to scale current computing designs is reaching a breaking point, and chipmakers such as Intel, Qualcomm and AMD are putting their brains together on an alternate architecture to push computing forward. The chipmakers are coalescing around the new concept of sparse computing, which involves bringing computing to data... Read more…

QuEra’s Quest: Build a Flexible Neutral Atom-based Quantum Computer

November 23, 2022

Last month, QuEra Computing began providing access to its 256-qubit, neutral atom-based quantum system, Aquila, from Amazon Braket. Founded in 2018, and built on technology developed at Harvard and MIT, QuEra, is one of Read more…

AWS Solution Channel

Shutterstock 1648511269

Avoid overspending with AWS Batch using a serverless cost guardian monitoring architecture

Pay-as-you-go resources are a compelling but daunting concept for budget conscious research customers. Uncertainty of cloud costs is a barrier-to-entry for most, and having near real-time cost visibility is critical. Read more…

 

shutterstock_1431394361

AI and the need for purpose-built cloud infrastructure

Modern AI solutions augment human understanding, preferences, intent, and even spoken language. AI improves our knowledge and understanding by delivering faster, more informed insights that fuel transformation beyond anything previously imagined. Read more…

SC22’s ‘HPC Accelerates’ Plenary Stresses Need for Collaboration

November 21, 2022

Every year, SC has a theme. For SC22 – held last week in Dallas – it was “HPC Accelerates”: a theme that conference chair Candace Culhane said reflected “how supercomputing is continuously changing the world by Read more…

Chipmakers Looking at New Architecture to Drive Computing Ahead

November 23, 2022

The ability to scale current computing designs is reaching a breaking point, and chipmakers such as Intel, Qualcomm and AMD are putting their brains together on an alternate architecture to push computing forward. The chipmakers are coalescing around the new concept of sparse computing, which involves bringing computing to data... Read more…

QuEra’s Quest: Build a Flexible Neutral Atom-based Quantum Computer

November 23, 2022

Last month, QuEra Computing began providing access to its 256-qubit, neutral atom-based quantum system, Aquila, from Amazon Braket. Founded in 2018, and built o Read more…

SC22’s ‘HPC Accelerates’ Plenary Stresses Need for Collaboration

November 21, 2022

Every year, SC has a theme. For SC22 – held last week in Dallas – it was “HPC Accelerates”: a theme that conference chair Candace Culhane said reflected Read more…

Quantum – Are We There (or Close) Yet? No, Says the Panel

November 19, 2022

For all of its politeness, a fascinating panel on the last day of SC22 – Quantum Computing: A Future for HPC Acceleration? – mostly served to illustrate the Read more…

RISC-V Is Far from Being an Alternative to x86 and Arm in HPC

November 18, 2022

One of the original RISC-V designers this week boldly predicted that the open architecture will surpass rival chip architectures in performance. "The prediction is two or three years we'll be surpassing your architectures and available performance with... Read more…

Gordon Bell Special Prize Goes to LLM-Based Covid Variant Prediction

November 17, 2022

For three years running, ACM has awarded not only its long-standing Gordon Bell Prize (read more about this year’s winner here!) but also its Gordon Bell Spec Read more…

2022 Gordon Bell Prize Goes to Plasma Accelerator Research

November 17, 2022

At the awards ceremony at SC22 in Dallas today, ACM awarded the 2022 ACM Gordon Bell Prize to a team of researchers who used four major supercomputers – inclu Read more…

Gordon Bell Nominee Used LLMs, HPC, Cerebras CS-2 to Predict Covid Variants

November 17, 2022

Large language models (LLMs) have taken the tech world by storm over the past couple of years, dominating headlines with their ability to generate convincing hu Read more…

Nvidia Shuts Out RISC-V Software Support for GPUs 

September 23, 2022

Nvidia is not interested in bringing software support to its GPUs for the RISC-V architecture despite being an early adopter of the open-source technology in its GPU controllers. Nvidia has no plans to add RISC-V support for CUDA, which is the proprietary GPU software platform, a company representative... Read more…

RISC-V Is Far from Being an Alternative to x86 and Arm in HPC

November 18, 2022

One of the original RISC-V designers this week boldly predicted that the open architecture will surpass rival chip architectures in performance. "The prediction is two or three years we'll be surpassing your architectures and available performance with... Read more…

AWS Takes the Short and Long View of Quantum Computing

August 30, 2022

It is perhaps not surprising that the big cloud providers – a poor term really – have jumped into quantum computing. Amazon, Microsoft Azure, Google, and th Read more…

Chinese Startup Biren Details BR100 GPU

August 22, 2022

Amid the high-performance GPU turf tussle between AMD and Nvidia (and soon, Intel), a new, China-based player is emerging: Biren Technology, founded in 2019 and headquartered in Shanghai. At Hot Chips 34, Biren co-founder and president Lingjie Xu and Biren CTO Mike Hong took the (virtual) stage to detail the company’s inaugural product: the Biren BR100 general-purpose GPU (GPGPU). “It is my honor to present... Read more…

Tesla Bulks Up Its GPU-Powered AI Super – Is Dojo Next?

August 16, 2022

Tesla has revealed that its biggest in-house AI supercomputer – which we wrote about last year – now has a total of 7,360 A100 GPUs, a nearly 28 percent uplift from its previous total of 5,760 GPUs. That’s enough GPU oomph for a top seven spot on the Top500, although the tech company best known for its electric vehicles has not publicly benchmarked the system. If it had, it would... Read more…

AMD Thrives in Servers amid Intel Restructuring, Layoffs

November 12, 2022

Chipmakers regularly indulge in a game of brinkmanship, with an example being Intel and AMD trying to upstage one another with server chip launches this week. But each of those companies are in different positions, with AMD playing its traditional role of a scrappy underdog trying to unseat the behemoth Intel... Read more…

JPMorgan Chase Bets Big on Quantum Computing

October 12, 2022

Most talk about quantum computing today, at least in HPC circles, focuses on advancing technology and the hurdles that remain. There are plenty of the latter. F Read more…

UCIe Consortium Incorporates, Nvidia and Alibaba Round Out Board

August 2, 2022

The Universal Chiplet Interconnect Express (UCIe) consortium is moving ahead with its effort to standardize a universal interconnect at the package level. The c Read more…

Leading Solution Providers

Contributors

Using Exascale Supercomputers to Make Clean Fusion Energy Possible

September 2, 2022

Fusion, the nuclear reaction that powers the Sun and the stars, has incredible potential as a source of safe, carbon-free and essentially limitless energy. But Read more…

Nvidia, Qualcomm Shine in MLPerf Inference; Intel’s Sapphire Rapids Makes an Appearance.

September 8, 2022

The steady maturation of MLCommons/MLPerf as an AI benchmarking tool was apparent in today’s release of MLPerf v2.1 Inference results. Twenty-one organization Read more…

Not Just Cash for Chips – The New Chips and Science Act Boosts NSF, DOE, NIST

August 3, 2022

After two-plus years of contentious debate, several different names, and final passage by the House (243-187) and Senate (64-33) last week, the Chips and Science Act will soon become law. Besides the $54.2 billion provided to boost US-based chip manufacturing, the act reshapes US science policy in meaningful ways. NSF’s proposed budget... Read more…

SC22 Unveils ACM Gordon Bell Prize Finalists

August 12, 2022

Courtesy of the schedule for the SC22 conference, we now have our first glimpse at the finalists for this year’s coveted Gordon Bell Prize. The Gordon Bell Pr Read more…

Intel Is Opening up Its Chip Factories to Academia

October 6, 2022

Intel is opening up its fabs for academic institutions so researchers can get their hands on physical versions of its chips, with the end goal of boosting semic Read more…

AMD Previews 400 Gig Adaptive SmartNIC SOC at Hot Chips

August 24, 2022

Fresh from finalizing its acquisitions of FPGA provider Xilinx (Feb. 2022) and DPU provider Pensando (May 2022) ), AMD previewed what it calls a 400 Gig Adaptive smartNIC SOC yesterday at Hot Chips. It is another contender in the increasingly crowded and blurry smartNIC/DPU space where distinguishing between the two isn’t always easy. The motivation for these device types... Read more…

Google Program to Free Chips Boosts University Semiconductor Design

August 11, 2022

A Google-led program to design and manufacture chips for free is becoming popular among researchers and computer enthusiasts. The search giant's open silicon program is providing the tools for anyone to design chips, which then get manufactured. Google foots the entire bill, from a chip's conception to delivery of the final product in a user's hand. Google's... Read more…

AMD’s Genoa CPUs Offer Up to 96 5nm Cores Across 12 Chiplets

November 10, 2022

AMD’s fourth-generation Epyc processor line has arrived, starting with the “general-purpose” architecture, called “Genoa,” the successor to third-gen Eypc Milan, which debuted in March of last year. At a launch event held today in San Francisco, AMD announced the general availability of the latest Epyc CPUs with up to 96 TSMC 5nm Zen 4 cores... Read more…

  • arrow
  • Click Here for More Headlines
  • arrow
HPCwire