Tackling the Power and Energy Wall for Future HPC Systems

By Performance and Architecture Lab (PAL) at PNNL

December 17, 2013

A Perspective from the Paci fic Northwest National Laboratory*

As the cost of powering a supercomputer or a datacenter increases, next generation exascale systems need to be considerably more power- and energy-efficient than current supercomputers to be of practical use. Constrained power consumption (20-25MW for the entire system is the target that the DOE Office of Science gave to the HPC community) is one of the limiting factors on the road to achieve sustainable performance at exascale. In fact, the power challenge is so fundamental that other challenges can be reduced to power limitations. For example, operating at near-threshold voltage (NTV) in order to perform computation within a given power budget may considerably increase the soft-error rate (resilience challenge). Unlike petascale systems, where the primary concern was performance, exascale systems need to climb the power and energy walls in order to deliver sustainable exaflops performance. At the Pacifi c Northwest Laboratory (PNNL) we are exploring holistically energy and power efficiency aspects at all levels of granularity, from processor architecture to system integration. We are also tackling the power and energy problems from several angles, from system software and programming models to performance and power modeling of scientifi c applications and extreme scale systems.

PNNL Research Areas Fig1

PNNL’s computing facilities, such as its Institutional HPC system (PIC), and an earlier testbed, the Energy Smart Data Center (ESDC), provide research platforms to address what-if questions related to the use of suitable datacenter metrics that are meaningful to the HPC community. The measurement harness of the ESDC entailed over thousand out-of-band sensors comprising power, flow, pressure and temperature at the machine room and at the IT equipment. PIC is another example that substantiates our integrated datacenter vision to drive energy efficiency research. This system is housed in a geothermally cooled datacenter with rear-door heat exchangers. The facility is instrumented at the machine room and system level, providing insight into macro-level machine room power efficiencies and micro-level energy efficiencies at the server and mother-board component levels.

Despite its importance for future exascale systems, power is still not considered a first-class citizen, which complicates the development of power-aware software algorithms. In PNNL’s vision, power should be considered a resource, just as processing elements or memory modules, and should be managed as such by the system software. System software must be able to precisely measure (in-band) power resource utilization, i.e., how much power is consumed by each system component at any given time. More importantly, the system software should adapt the application to the contingent execution environment, e.g, by allocating sustained power to threads on the application’s critical path or promptly moving idle cores to low-power states. The design and development of such self-aware/self-adaptive system software is an active research area at PNNL. We recently analyzed the power characteristics of scientifi c applications from the DOE ASCR’s Exascale Co-Design Center and, in general, in the HPC community to identify opportunities for power savings. Given the lack of in-band, fine-grained (both in space and time) power sensors, we develop an accurate per-core proxy power sensor model that estimates the active power of each core by inspecting the cores’ activity. We use statistical regression techniques to formulate closed-form expressions for the estimated core and system power consumption. These techniques enable us to develop power-aware algorithms and characterize applications running even on non-instrumented compute nodes. Our experiments show that processes in the same application may not have the same power profi le and/or may alternate high-power with low-power phases independently from one another. These alternating behaviors raise opportunities for shifting power towards computing-demanding processes, hereby saving power without diminishing performance.

There is a strong agreement among researchers on the increasing cost of data movement with respect to computation. This ratio will further increase in future systems that will approach NTV operation levels: the energy consumption of a double precision register-to-register floating point operation is expected to decrease by 10x by 2018. The energy cost of moving data from memory to processor is not expected to follow the same trend, hence the relative energy cost of data movement with respect to performing a register-to-register operation will increase (energy wall — analogous to the memory wall). In a recent study we modeled the energy cost of moving data across the memory hierarchy of current systems and analyzed the energy cost of data movement for scientifi c applications. In this study, we answer several important questions such as what is the amount of energy spent in data movement with respect to the total energy consumption of an application or what is the dominant component of data movement energy for current and future parallel applications. Our results show that the energy cost of data movement impact di fferently on each application, ranging from 18% to 40%. This percentage might increase in the future, as the energy cost of performing computation decreases. To avoid such scenario, new technologies, such as Processing-In- Memory, Non-Volatile RAM and 3D-stacked memory, become essential for the development of sustainable exascale computing. We also noticed that the energy spent in resolving data dependency, speculation and out-of-order scheduling of instructions accounts for a considerable part of the total dynamic energy, between 22% and 35%. This cost can be reduced with simpler processor core designs that are more energy efficient.

Given the increasing complexity of future exascale applications and systems, designers need new sophisticated tools to navigate the design space. These tools must capture a range of metrics that are of interest to system and application designers, including performance and power consumption. PNNL has historically developed application-specific performance tools that model the evolution of parallel applications. While these models have shown themselves to be powerful tools for understanding the mapping of applications to complex system architectures, the metrics of interest are expanding to include power consumption as well. To this end, PNNL researchers have developed a methodology for the modeling of performance and power in concert that builds upon its experience of co-designing systems and applications. This modeling capability has been developed along three axes. The first is the deployment of a workload-specific quantitative power modeling capability. Such power models accurately capture workload phases, their impact on power consumption, and how they are impacted by system architecture and con figuration (e.g., processor clock speed). The second axis is the integration of the performance and power modeling methodologies. To this end, it is critical that both modeling methods operated at the same conceptual level. In other words, application phases or components that are captured in one model must be also reflected in the other so that trade-o ffs between power and performance may be captured and quantifi ed. The last axis of development involves integrating these models with our self-aware/self-adaptive software system that will provide mechanisms for dynamically optimizing ongoing application execution. We have developed the concept of Energy Templates, which are a mechanism for passing application-specifi c behavioral information to the underlying runtime layers. Energy Templates capture per-core idle/busy states, as well as the amount of time each core expects to remain in each state, allowing runtime software to determine appropriate opportunities to exercise power saving features provided by the hardware/software platform (e.g., Dynamic Voltage and Frequency Scaling — DVFS) without negatively impacting performance. By proactively using application-speci fic information, Energy Templates are able to exploit energy savings opportunities that are not available to mechanisms that are not application-aware.

The research at PNNL is also being applied within the new DARPA program in the Power Efficiency Revolution of Embedded Technologies (PERFECT). We see that technologies being developed both for high performance computing and embedded systems are fundamentally the same. These may well converge in the future, and thus common tools and techniques can be developed that encompass both. Within PERFECT PNNL researchers are developing a coherent framework that is able to both empirically analyze current systems and predictively assess future technologies.

Finally, PNNL’s research extends to the datacenters: this research direction is approached in an integrated fashion where IT power consumption for applications of interest to the DOE is correlated with the power consumption of the supporting infrastructure. An integrated approach allows the researcher to formulate what-if questions in an HPC setting such as the applicability and efficacy of novel cooling solutions (e.g., spray cooling) at the heat source vs. a traditional global cooling solution.

Overall, PNNL is actively participating in (and in many cases leading) several DOE and DARPA projects, as well as internal projects, that aim at understanding the impact of the power and energy walls on exascale systems and deploying power- and energy-aware solutions at all levels of the system and application design and optimization. The insights gained throughout these efforts and projects will contribute towards the design of power- and energy-efficient exascale systems.

*The following PNNL researchers contributed to this piece: Adolfy Hoisie, Kevin Barker, Roberto Gioiosa, Darren J. Kerbyson, Gokcen Kestor, Joseph Manzano, Andres Marquez, Shuaiwen Song, Nathan Tallent, Antonino Tumeo, Abhinav Vishnu

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