The Future of Accelerator Programming

By Kamil Rocki and Martin Burtscher

January 9, 2014

Many of the latest supercomputers are based on accelerators, including the two fastest systems according to the 11/2013 TOP500 list. Accelerators are also becoming widespread in PCs and are even starting to appear in handheld devices, which will further boost the interest in accelerator programming.

This broad adoption is the result of high performance, good energy efficiency, and low price. For example, comparing a Xeon E5-2687W CPU to a GTX 680 GPU, both of which were released in March 2012, we find that the GPU started out four times cheaper, has eight times more single-precision performance and four times more main-memory bandwidth, and provides over thirty times as much performance per dollar and six times as much performance per watt. Based on these numbers, accelerators should be used everywhere and all the time. So why aren’t they?

There are two main difficulties with accelerators. First, they can only execute certain types of programs efficiently, in particular programs with sufficient parallelism, data reuse, and regularity in their control flow and memory access patterns. Second, it is harder to write effective software for accelerators than for CPUs because of architectural disparities such as very wide parallelism, exposed memory hierarchies, lockstep execution, and memory-access coalescing. Several new programming languages and extensions thereof have been proposed to hide these aspects to various degrees and thus make it easier to program accelerators.

The initial attempts to use GPUs, which are currently the most prominent type of accelerator, for speeding up non-graphics programs were cumbersome and required expressing the computation in form of shader code that only supported limited control flow and no integer operations. Gradually, these constraints were lifted, making GPUs more general-purpose computing devices and enabling non-graphics-experts to program them. The biggest step in this direction came with the release of the CUDA programming language. It extends C/C++ with additional qualifiers and keywords as well as library functions and a mechanism to launch code sections, called kernels, on a GPU.

The rapid adoption of CUDA, combined with that fact that it is proprietary and the complexity of writing good CUDA code, triggered the creation of several other programming approaches for accelerators, including OpenCL, C++ AMP, and OpenACC. OpenCL is the non-proprietary counterpart of CUDA and is backed by many large companies. It is not restricted to NVIDIA GPUs but also supports AMD GPUs, multicore CPUs, MICs (Intel’s Xeon Phi), DSPs, and FPGAs, making it very portable. However, just like CUDA, it is very low level and requires the software developer to explicitly orchestrate data movement, select where variables live in the memory hierarchy, and manually express parallelism in the code. C++ Accelerated Massive Parallelism (C++ AMP) operates at a medium level. It allows expressing data parallelism directly in C++ and hides all low-level code from the programmer. Parallel “for each” statements encapsulate parallel code. C++ AMP is tied to Windows, does not (yet) support CPUs, and suffers from startup overhead, making it impractical for accelerating short-running code sections.

OpenACC is a very high-level approach that allows programmers to annotate their code using pragmas to inform the compiler which code sections to accelerate, e.g., by offloading them to a GPU. The idea is similar to how OpenMP can be used to parallelize CPU programs. In fact, there are efforts underway to merge the two approaches. OpenACC is still maturing and currently only supported by a few compilers.

To predict how accelerator programming might develop from this point forward, it may be helpful to study how other acceleration hardware has evolved in the past. For example, some early high-end PCs contained an extra chip, called a co-processor, to accelerate floating-point (FP) calculations. Later, this co-processor was combined with the CPU on the same die and is now fully integrated with the integer processing core. Only separate FP registers and ALUs remain. The much more recently added SIMD support (including MMX, SSE, AltiVec, and AVX) did not start out on a separate chip but is now also fully integrated in the core. Just like the floating-point instructions, SIMD instructions operate on separate registers and ALUs.

Interestingly, the programmer’s view of these two types of instructions is surprisingly different. The floating-point operations and data types have been standardized long ago (IEEE 754) and are now ubiquitous. They are directly available in high-level languages through normal arithmetic operations and built-in 32-bit single-precision and 64-bit double-precision types. In contrast, no standard exists for SIMD instructions, and their existence is largely hidden from programmers. It is left to the compiler to ‘vectorize’ the code and employ these instructions. Developers wishing to use SIMD instructions explicitly have to resort to compiler-specific macros that are not portable.

Since GPUs and MICs obtain their high performance through SIMD-like execution, we believe accelerators are more likely to track the evolution of SIMD- than FP-instruction support. Another similarity to SIMD, and a key factor that made CUDA so successful, is that CUDA hides the SIMD aspect of the GPU hardware and allows the programmer to think in terms of individual threads operating on scalar data elements rather than warps operating on vectors. Hence, accelerators will undoubtedly also be moved onto the CPU chip, but we surmise that their code will not be seamlessly interwoven with CPU code nor will the accelerators’ hardware-supported data types be made explicitly available to the programmers.

Some accelerators have already been combined with conventional processing cores on the same chip, including on AMD’s APUs (as used in the Xbox One), Intel’s processors with HD Graphics, and NVIDIA’s Tegra SoC. However, accelerators will probably remain separate cores because it is difficult to fuse accelerator and conventional cores to the degree that was possible with FP and SIMD instructions, i.e., to ‘reduce’ the accelerator to just a set of separate registers and ALUs in the general-purpose core. After all, accelerators are so fast, parallel, and energy efficient because they are based on dissimilar architectural tradeoffs, such as incoherent caches, very different pipeline designs, GDDR5 memory, and an order of magnitude more registers and multithreading. Hence, the complexity of having to run separate accelerator code will remain. As even cores on the same die tend to share no more than the bottom of the memory hierarchy, data transfers between CPU and accelerator cores will possibly become faster but also remain a bottleneck.

The explicit orchestration of data exchanges between devices is a significant source of errors and a substantial burden on programmers. For short kernels, it is often the case that more code needs to be written to transfer data back and forth than to express the actual computation. Eliminating this burden is one of the primary benefits of higher-level programming approaches such as C++ AMP and OpenACC. Even low-level approaches have been addressing this problem. For example, streamlined and unified memory addressing is one of the major improvements in the latest CUDA and OpenCL releases and NVIDIA GPU hardware. Yet, to achieve good performance, some help by the programmer is generally needed, even in very high-level approaches like OpenACC. In particular, locality-aware memory allocation and data migration often have to be handled manually.

Unfortunately, any ease provided by such improvements may only turn out to be a partial solution. Based on the assumption that future microprocessors will be similar to today’s (small) supercomputers, it is likely that they will contain many more cores than can be served by a shared (NUMA) memory system. Instead, we believe there will be clusters of cores on each die where each cluster has its own memory, possibly stacked on top of the cores in a 3D design. The clusters communicate with each other via an on-chip network using a protocol akin to MPI. We do not believe this is farfetched as Intel just announced that it will include networking capabilities in their future Xeon chips, which is a step in this direction. Hence, it is likely that future chips will become more and more heterogeneous, comprising latency- and throughput-optimized cores, NICs, encryption and compression cores, FPGAs, etc.

That raises the all-important question of how to program such devices. We think the answer is surprisingly similar to how today’s multiple CPU cores, SIMD instruction set extensions, and compute accelerators are being used. Basically, there are three levels at which this is done, which we refer to as libraries, automated tools, and do-it-yourself. The library approach is the simplest and works by calling functions in a library that has been accelerated by someone else. Many of the latest math libraries belong to this category. As long as most of the computation takes place inside the library code, this approach is very successful. It allows a few expert library writers to enable the acceleration of a large number of applications.

The automated tools approach is the approach taken by C++ AMP and OpenACC, where the compiler has to do the heavy lifting. The success of this approach depends on the quality and sophistication of the available software tools and, as mentioned, often needs help from the programmer. Nevertheless, most developers can reasonably quickly achieve positive results with this approach, which is not limited to predetermined functions in a library. This is perhaps reminiscent of how a few expert teams code up the inner workings of SQL, which then allows a large number of ‘regular’ programmers to benefit from the optimizations and know-how that the experts encoded.

Finally, the do-it-yourself approach is represented by CUDA and OpenCL, which give the programmer full control over and access to almost every aspect of the accelerator. If implemented well, the resulting code can outperform the other two approaches. However, this comes at the cost of a steep learning curve, lots of extra code that needs to be written, and a slew of additional possibilities for bugs. Ever improving debugging and programming environments will help alleviate these problems, but only to a degree. Hence, this approach is primarily useful for expert programmers, such as those writing the aforementioned libraries and tools.

Since it is trivial to use, programmers will employ the library approach whenever possible. However, this hinges on the availability of appropriate library functions, which are easy to provide in well-defined and mature domains such as standard matrix operations (BLAS) but hard to do for emerging areas or unstructured computations. In the absence of adequate libraries, a programmer’s second choice will be the tools approach, assuming that the tools will be mature. Any computations that are not available in a library, do not demand the highest performance, and are supported by the compiler will likely be coded up using the tools approach. For the remaining cases, the do-it-yourself approach will have to be used. Since OpenCL incorporates the successful ideas that CUDA introduced, is non-proprietary, and supports a large range of hardware, we believe OpenCL or a derivative of it will start dominating this domain akin to how MPI has become the de facto standard for distributed-memory programming.

Taking the union of the hardware features and evolution outlined above, future processor chips might contain multiple clusters with their own memory, each cluster consists of a set of cores where not all cores necessarily have the same capabilities, each multithreaded compute core comprises a large number of processing elements (i.e., functional units or ALUs), and each processing element may be able to perform SIMD operations. Even though actual chips might not include all of the above, they all share a key similarity, namely a hierarchy of distinct parallelization levels. To effectively and portably program such a system, we propose what we call the “copious-parallelism” technique. It is a generalization of how MPI programs are typically explicitly written to adapt to the number of available compute nodes or how OpenMP code implicitly adapts to the number of available cores (or threads).

The main idea behind copious parallelism, and the reason for its name, is to provide ample and parameterizable parallelism for each level. The parameterization makes it possible to decrease the parallelization at any level to match the hardware parallelism at that level. For example, on a shared-memory system, the highest level of parallelization is not necessary and should be set to just one “cluster”. Similarly, in a core where the functional units are unable to perform SIMD instructions, the parameter determining the SIMD width should be set to one. This technique is able to exploit the common features of current multicore CPUs, GPUs, MICs, and other devices as well as likely future architectures. While it is definitely harder to write software in this manner, copious parallelism makes it possible to extract high performance from a broad range of computing devices with just a single code base.

We have tested this approach on a direct n-body simulation [ref]. We wrote a single copious-parallelism implementation in OpenCL and assessed it on four very different architectures: an NVIDIA GeForce Titan GPU, an AMD Radeon 7970 GPU, an Intel Xeon E5-2690 multicore CPU, and an Intel Xeon Phi 5110P MIC. Given our FLOP mix of 54% non-FMA operations, the copious-parallelism code achieves 75% of the theoretical peak performance on the Titan, 95% on the Radeon, 80.5% on the CPU, and 80% on the MIC. While this is only one example, the results are extremely encouraging. In fact, we believe the copious-parallelism technique may well be and remain for quite some time the only portable high-performance approach for programming current and future accelerated systems.

About the Authors

kamilKamil Rocki is a postdoctoral researcher at IBM Research. Prior to joining Almaden Research Center in California he has spent 5 years in Japan at the University of Tokyo where he graduated with a PhD degree in Information Science. Before that he received his M.Sc. and B.Sc. degrees in Computer Science from Warsaw University of Technology. His current research focuses on high performance parallel algorithms and hardware design. Other interests include supercomputing, AI, computer vision and robotics. He has been working in the field of GPGPU programming for the past 8 years.

 

 
martinMartin Burtscher is Associate Professor in the Department of Computer Science at Texas State University. He received the BS/MS degree in computer science from the Swiss Federal Institute of Technology (ETH) Zurich and the Ph.D. degree in computer science from the University of Colorado at Boulder. Martin’s research interests include efficient parallelization of programs for GPUs and multicore CPUs, automatic performance assessment and optimization, and high-speed data compression. He is a senior member of the IEEE, its Computer Society, and the ACM. Martin has co-authored over 75 peer-reviewed scientific publications, including a book chapter in NVIDIA’s GPU Computing Gems, is the recipient of an NVIDIA Academic Partnership award, and is the PI of a CUDA Teaching Center.

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

Musk’s Latest Startup Eyes Brain-Computer Links

April 21, 2017

Elon Musk, the auto and space entrepreneur and severe critic of artificial intelligence, is forming a new venture that reportedly will seek to develop an interface between the human brain and computers. Read more…

By George Leopold

MIT Mathematician Spins Up 220,000-Core Google Compute Cluster

April 21, 2017

On Thursday, Google announced that MIT math professor and computational number theorist Andrew V. Sutherland had set a record for the largest Google Compute Engine (GCE) job. Sutherland ran the massive mathematics workload on 220,000 GCE cores using preemptible virtual machine instances. Read more…

By Tiffany Trader

NERSC Cori Shows the World How Many-Cores for the Masses Works

April 21, 2017

As its mission, the high performance computing center for the U.S. Department of Energy Office of Science, NERSC (the National Energy Research Supercomputer Center), supports a broad spectrum of forefront scientific research across diverse areas that includes climate, material science, chemistry, fusion energy, high-energy physics and many others. Read more…

By Rob Farber

Nvidia P100 Shows 1.3-2.3x Speedup Over K80 GPU on Financial Apps

April 20, 2017

When it comes to the true performance of the latest silicon, every end user knows that the best processor is the one that works best for their application. Read more…

By Tiffany Trader

HPE Extreme Performance Solutions

Remote Visualization Optimizing Life Sciences Operations and Care Delivery

As patients continually demand a better quality of care and increasingly complex workloads challenge healthcare organizations to innovate, investing in the right technologies is key to ensuring growth and success. Read more…

Quantum Adds Global Smarts to StorNext File System

April 20, 2017

Companies that use Quantum’s StorNext platform to store massive amounts of data this week got a glimpse of new storage capabilities that should make it easier to access their data horde from anywhere in the world. Read more…

By Alex Woodie

Scaling an HPC Career in Nepal Can Be a Steep Climb

April 20, 2017

Umesh Upadhyaya works as an IT Associate at the International Centre for Integrated Mountain Development (ICIMOD) in Nepal, which supports the country’s one and only HPC facility. He is directly involved in an initiative that focuses on climate change and atmosphere modeling Read more…

By Nages Sieslack

Hyperion (IDC) Paints a Bullish Picture of HPC Future

April 20, 2017

Hyperion Research – formerly IDC’s HPC group – yesterday painted a fascinating and complicated portrait of the HPC community’s health and prospects at the HPC User Forum held in Albuquerque, NM. HPC sales are up and growing ($22 billion, all HPC segments, 2016). Read more…

By John Russell

Intel Open Sources All Lustre Work, Brent Gorda Exits

April 19, 2017

In a letter to the Lustre community posted on the Intel website, Vice President of Intel's Data Center Group Trish Damkroger writes that effective immediately the company will be contributing all Lustre development to the open source community. Damkroger also announced that Brent Gorda, General Manager, High Performance Data Division at Intel is leaving the company. Read more…

By Tiffany Trader

NERSC Cori Shows the World How Many-Cores for the Masses Works

April 21, 2017

As its mission, the high performance computing center for the U.S. Department of Energy Office of Science, NERSC (the National Energy Research Supercomputer Center), supports a broad spectrum of forefront scientific research across diverse areas that includes climate, material science, chemistry, fusion energy, high-energy physics and many others. Read more…

By Rob Farber

Hyperion (IDC) Paints a Bullish Picture of HPC Future

April 20, 2017

Hyperion Research – formerly IDC’s HPC group – yesterday painted a fascinating and complicated portrait of the HPC community’s health and prospects at the HPC User Forum held in Albuquerque, NM. HPC sales are up and growing ($22 billion, all HPC segments, 2016). Read more…

By John Russell

Knights Landing Processor with Omni-Path Makes Cloud Debut

April 18, 2017

HPC cloud specialist Rescale is partnering with Intel and HPC resource provider R Systems to offer first-ever cloud access to Xeon Phi "Knights Landing" processors. The infrastructure is based on the 68-core Intel Knights Landing processor with integrated Omni-Path fabric (the 7250F Xeon Phi). Read more…

By Tiffany Trader

CERN openlab Explores New CPU/FPGA Processing Solutions

April 14, 2017

Through a CERN openlab project known as the ‘High-Throughput Computing Collaboration,’ researchers are investigating the use of various Intel technologies in data filtering and data acquisition systems. Read more…

By Linda Barney

DOE Supercomputer Achieves Record 45-Qubit Quantum Simulation

April 13, 2017

In order to simulate larger and larger quantum systems and usher in an age of “quantum supremacy,” researchers are stretching the limits of today’s most advanced supercomputers. Read more…

By Tiffany Trader

Penguin Takes a Run at the Big Cloud Providers

April 12, 2017

HPC specialist Penguin Computing recently re-ran benchmarks from a study of its larger brethren and says the results show its ‘public cloud’ – Penguin on Demand (POD) – is among the leaders in cost and performance. Read more…

By John Russell

Nvidia Responds to Google TPU Benchmarking

April 10, 2017

Nvidia highlights strengths of its newest GPU silicon in response to Google's report on the performance and energy advantages of its custom tensor processor. Read more…

By Tiffany Trader

HPC and the Colocation Datacenter – a Bridge Too Far?

April 7, 2017

A more standardised HPC platform approach is making the running of HPC projects within increasing financial reach. Read more…

By Clive Longbottom, Quocirca

Google Pulls Back the Covers on Its First Machine Learning Chip

April 6, 2017

This week Google released a report detailing the design and performance characteristics of the Tensor Processing Unit (TPU), its custom ASIC for the inference phase of neural networks (NN). Read more…

By Tiffany Trader

Quantum Bits: D-Wave and VW; Google Quantum Lab; IBM Expands Access

March 21, 2017

For a technology that’s usually characterized as far off and in a distant galaxy, quantum computing has been steadily picking up steam. Read more…

By John Russell

Trump Budget Targets NIH, DOE, and EPA; No Mention of NSF

March 16, 2017

President Trump’s proposed U.S. fiscal 2018 budget issued today sharply cuts science spending while bolstering military spending as he promised during the campaign. Read more…

By John Russell

HPC Compiler Company PathScale Seeks Life Raft

March 23, 2017

HPCwire has learned that HPC compiler company PathScale has fallen on difficult times and is asking the community for help or actively seeking a buyer for its assets. Read more…

By Tiffany Trader

Nvidia Responds to Google TPU Benchmarking

April 10, 2017

Nvidia highlights strengths of its newest GPU silicon in response to Google's report on the performance and energy advantages of its custom tensor processor. Read more…

By Tiffany Trader

For IBM/OpenPOWER: Success in 2017 = (Volume) Sales

January 11, 2017

To a large degree IBM and the OpenPOWER Foundation have done what they said they would – assembling a substantial and growing ecosystem and bringing Power-based products to market, all in about three years. Read more…

By John Russell

CPU-based Visualization Positions for Exascale Supercomputing

March 16, 2017

In this contributed perspective piece, Intel’s Jim Jeffers makes the case that CPU-based visualization is now widely adopted and as such is no longer a contrarian view, but is rather an exascale requirement. Read more…

By Jim Jeffers, Principal Engineer and Engineering Leader, Intel

TSUBAME3.0 Points to Future HPE Pascal-NVLink-OPA Server

February 17, 2017

Since our initial coverage of the TSUBAME3.0 supercomputer yesterday, more details have come to light on this innovative project. Of particular interest is a new board design for NVLink-equipped Pascal P100 GPUs that will create another entrant to the space currently occupied by Nvidia's DGX-1 system, IBM's "Minsky" platform and the Supermicro SuperServer (1028GQ-TXR). Read more…

By Tiffany Trader

Leading Solution Providers

Tokyo Tech’s TSUBAME3.0 Will Be First HPE-SGI Super

February 16, 2017

In a press event Friday afternoon local time in Japan, Tokyo Institute of Technology (Tokyo Tech) announced its plans for the TSUBAME3.0 supercomputer, which will be Japan’s “fastest AI supercomputer,” Read more…

By Tiffany Trader

IBM Wants to be “Red Hat” of Deep Learning

January 26, 2017

IBM today announced the addition of TensorFlow and Chainer deep learning frameworks to its PowerAI suite of deep learning tools, which already includes popular offerings such as Caffe, Theano, and Torch. Read more…

By John Russell

Is Liquid Cooling Ready to Go Mainstream?

February 13, 2017

Lost in the frenzy of SC16 was a substantial rise in the number of vendors showing server oriented liquid cooling technologies. Three decades ago liquid cooling was pretty much the exclusive realm of the Cray-2 and IBM mainframe class products. That’s changing. We are now seeing an emergence of x86 class server products with exotic plumbing technology ranging from Direct-to-Chip to servers and storage completely immersed in a dielectric fluid. Read more…

By Steve Campbell

BioTeam’s Berman Charts 2017 HPC Trends in Life Sciences

January 4, 2017

Twenty years ago high performance computing was nearly absent from life sciences. Today it’s used throughout life sciences and biomedical research. Genomics and the data deluge from modern lab instruments are the main drivers, but so is the longer-term desire to perform predictive simulation in support of Precision Medicine (PM). There’s even a specialized life sciences supercomputer, ‘Anton’ from D.E. Shaw Research, and the Pittsburgh Supercomputing Center is standing up its second Anton 2 and actively soliciting project proposals. There’s a lot going on. Read more…

By John Russell

HPC Startup Advances Auto-Parallelization’s Promise

January 23, 2017

The shift from single core to multicore hardware has made finding parallelism in codes more important than ever, but that hasn’t made the task of parallel programming any easier. Read more…

By Tiffany Trader

HPC Technique Propels Deep Learning at Scale

February 21, 2017

Researchers from Baidu’s Silicon Valley AI Lab (SVAIL) have adapted a well-known HPC communication technique to boost the speed and scale of their neural network training and now they are sharing their implementation with the larger deep learning community. Read more…

By Tiffany Trader

US Supercomputing Leaders Tackle the China Question

March 15, 2017

Joint DOE-NSA report responds to the increased global pressures impacting the competitiveness of U.S. supercomputing. Read more…

By Tiffany Trader

IDG to Be Bought by Chinese Investors; IDC to Spin Out HPC Group

January 19, 2017

US-based publishing and investment firm International Data Group, Inc. (IDG) will be acquired by a pair of Chinese investors, China Oceanwide Holdings Group Co., Ltd. Read more…

By Tiffany Trader

  • arrow
  • Click Here for More Headlines
  • arrow
Share This