One Year, 7,000 Xeon Phi Cards: The TACC Experience

By Nicole Hemsoth

February 3, 2014

The Intel Xeon Phi, which was just branded and officially launched back in November 2012, is already behind some leading research at one of the U.S.’s premier scientific computing centers. According to leaders at the Texas Advanced Computing Center (TACC), the coprocessor has made significant bounds into a wider array of applications over the last year.

The Stampede supercomputer at the Texas Advanced Computing Center (TACC) was the first large-scale system to deploy the Phi at massive scale. We spoke with Dan Stanzione, acting director at TACC (replacing Jay Boisseau, who retired from the center in January) about the Dell-integrated system, which has around 100,000 processors and 2.2 petaflops of performance within the base Xeon system alone. In addition to this, Stampede has a number of specialized subsystems, including a large shared memory system, GPUs to support on-system visualization as well as GPU computing. The approximately 7,000 Xeon Phi cards added another 7.5 petaflops of performance, bringing the system to #7 on the most recent Top 500 list at around 10 petaflops.

The use cases for Xeon Phi at TACC have been most notable in a few key areas, including molecular dynamics for flu vaccine research, quantum chromodynamics and increasingly, weather forecasting, Stanzione says. However, their deployment of the cards was rather different than usual to begin with. Since they received Stampede nodes well in advance of the Phi cards, the team had to later install each card by hand—one for each of the nodes (although some are equipped with two). Aside from going through close to 150,000 screws, this meant that users were forced to skip the staging process that happens with new architectures.

For many users, instead of taking time on workstations and on small experimental clusters to kick the Phi tires, they jumped in at full scale. The benefit of this, however, was that Stanzione and his team were able to see the entire lifecycle of the Phi implementation. It started with very small experimental runs, but over time they’ve seen it catch on with a number of user groups, with some moving quickly into production and scaling up the size of their runs to tens of thousands of cores. Stanzione says they’ve seen Phi usage grow from 1 or 2 percent of the cycles each month to 10-20 percent.

“The Phi is one of several solutions (GPUs, FPGAs, APUs and others) focused on changing the power and performance curves that are the current trends in supercomputing. Transistors and operations are getting more efficient in every generation, but our demand for computation is growing faster than our power efficiency–so we still end up with substantially bigger systems that take more power,” said Stanzione. He made this point in the context of the Ranger system that Stampede stepped in for, noting that Stampede’s base system is about four times the compute power that Ranger was, but it’s also about twice the physical power and footprint of Ranger. “That’s not a curve we can stay on forever. The Xeon Phi is Intel’s approach to really changing these power and performance curves by giving us simpler cores with a simpler architecture but a lot more of them in the same size package.”

Stanzione continued, “Although we have the same power per transistor, we have a lot less power per floating point operation…the ARM, GPU and other folks are taking different approaches to that problem but we went with Phi. We went through all of them and looked carefully because although in any of these architectures you have much more parallelism on the chip you’re going to have to expose a lot more of the parallelism in your application, but the Phi was most familiar to the largest swath of our users—it’s the familiar x86 programming model; OpenMP for threading, MPI for task-based parallelism.”

“Whether you’re looking at GPUs or Xeon Phi that are both in the accelerator world now on a separate card and offloaded to the CPU, I think they both foreshadow what is coming in the future—the not so distant future—in the mainline processors. The work that we’re putting in now to optimize codes for these architectures is certainly going to pay off down the line as these become part of the mainline processors. So it’s not so much ‘should I adopt them;’ it’s whether you want to get a jump for the future.”

You can hear the full interview with Stanzione here.

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