New Research Advances Heterogenous 3D Chip Design

By Tiffany Trader

February 6, 2014

As transistors approach the limits of miniaturization, the rapid pace of progress in the microprocessor industry is destined to start declining unless researchers are successful in innovating alternative designs. The best and brightest minds of our time are hard at work developing the next generation of microprocessors so essential to supercomputers, handheld devices and worldwide communication systems. One of the researchers dedicated to extending these Moore’s law returns is Emre Salman, an assistant professor of computer and electrical engineering at Stony Brook University.

With funding from the National Science Foundation (NSF), Salman, who also directs Stony Brook’s Nanoscale Circuits and Systems (NanoCAS) Laboratory, is refining an approach called heterogeneous three-dimensional (3-D) integration. This emerging technology in which multiple wafers are stacked vertically has the potential to consume less power and provide higher performance than current two-dimensional chips.

“Today’s typical electronic system on a circuit board consists of multiple chips connected with wires that are at the millimeter and centimeter scale,” he explains. “These bulky connections not only slow down the circuit, but also consume power and reduce the reliability of the system.”

In 3-D technology, discrete chips, called tiers, are stacked on top of each other prior to being packaged. “Vertical connections that achieve communication among the tiers are now in the micrometer scale, and getting even shorter with advances in 3-D manufacturing technology, thereby consuming less power and providing more performance,” Salman explains. “Essentially, 3-D technology enables higher and heterogeneous integration at a smaller form factor.”

The approach is not without its challenges, like getting the multiple planes to work in harmony as a single unit. Researchers have spent more than a decade working to develop 3-D chip technology, but Salman says that most projects have focused on high performance and fairly homogeneous chips, such as microprocessors.

The 2011 edition of the International Technology Roadmap for Semiconductors (ITRS), which provides guidance for the field, says that, “the third phase and long term application of 3-D technology includes highly heterogeneous integration, where sensing and communication planes are stacked with conventional data processing and memory planes.”

This longer-term approach is what Salman and his team are focused on. It would extend the three-dimensional domain from high performance computing to relatively low power systems-on-chip (SoCs), which have capabilities beyond the scope of traditional general purpose processors. The result is the integration of multiple functions, including sensing, processing, storage and communication into a single 3-D chip. In other words, a single 3-D chip would have the ability to sense, process and store data using advanced algorithms, and then wirelessly transmit the data to another location.

“Numerous applications exist in health care, energy efficient mobile computing, and environmental control, since a smaller form factor can be achieved at lower power while offering significant computing resources,” he says. “Our fundamental objective is to develop a reliable 3-D analysis and design platform for these applications which will host future electronics systems that are increasingly more portable, can interact with the environment, consume low power, yet still offer significant computing capability.”

Salman is the recipient of an NSF Faculty Early Career Development (CAREER) award, which provides $453,809 in funding for the project over five years. The CAREER program recognizes junior faculty with promising careers who promote the integration of education and research.

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