NVIDIA Steers Roadmap Around GPU Bottlenecks

By Nicole Hemsoth

March 25, 2014

The GPU Technology Conference (GTC ’14) kicked off this morning in San Jose with NVIDIA CEO, Jen-Hsun Huang, opting to open the event with a preview of what’s ahead for GPUs in big data–and big computing. While the gaming and entertainment eye candy  one expects at GTC did indeed find its way into the mix, high performance computing, machine learning, computer vision and large-scale analytics talk set the tone for the year, leaving no room for doubt that the GPU maker is serious about its business for performance and efficiency-conscious mainstream enterprise and research users.

NVIDIA’s roadmap for GPU computing revolves around resolving some of the core bottlenecks that have always existed for accelerators in terms of data movement and memory capability. In this era of “big data,” the performance levels drop off with the addition of ever-larger data streams, even with innovations that have tried to get around this by letting the GPU crunch while data movement goes on in the background as with recent efforts around direct memory access (DMA).

NVIDIA’s answer to the data movement bottleneck is found in today’s announcement of NVLink, which is its newly announced chip-to-chip communication approach that lets the GPU talk on a dedicated line with other GPUs, as well as hook directly to the CPU along unified memory lines without the weight of PCIe—which even at its best in the current 3.0 state can’t compare to what they’ve cooked. In effect, this bundle of PCIe pipes with DMA acts much like an extension of high bandwidth (and proprietary, one should add) PCIe. It splits the efficiency and performance drain of pure PCIe into components instead of running both through the same pipes. The end result, said Huang during his keynote, is a 5-12x performance improvement over PCIe 3.0 and a 4x efficiency boost.

NVIDIA was reluctant to share a great deal in the way of detail, but in essence, NVLink is comprised of bi-directional 8-lane “bricks” which can be put together to get the bandwidth boost promised. The speed on each of the lanes is around 20 Gb/s for each brick. However, it appears that this will be the second generation of the interconnect instead with the first iteration sporting a four-lane highway, which will be found first in Pascal, which we’ll get to in a moment.

NVLink1

In the event that a user is hooked in with a CPU that doesn’t support NVLink, the same fast lane can be opened between GPUs as below.

NVLink2

This is the sort of development one might expect out of a research group led by interconnect wizard, Bill Dally. And it might seem that there would have to be a “catch” of some sort. Other than having to start from the ground in terms of building and investing in new motherboards and an ecosystem, it’s hard to see what some of the challenges might be at this point beyond which OEMs will go out of their way to meet the terms of the yet-unannounced licensing plan. While it may involve a new set of motherboards to contend with, the good news is the module, which is very small, can be snapped in to allow for the construction of very dense servers. Additionally, the programming model shouldn’t be its own bottleneck as NVLink looks very mich like PCIe, but with its own special DMA capabilities to allow software to adapt to it easily. NVIDIA notes that the first generation will not be memory coherent, users will have to hold out for the second iteration of NVLink, by which time there might be a chance for an ecosystem to develop around it.

All of this work starts to hum together around the 2016 timeframe with the addition of Pascal, which was announced today to fill in the gaps between now and Volta. Pascal, named after the famous mathematician, will provide unified memory and 3D memory in addition to sporting what will likely be the first generation of NVLink. As you can see, the current status of Maxwell is right on time, however NVIDIA declined questions about when that would be extended to meet the needs of the Tesla group.

NVPascal

One of the key features of Pascal is the addition of stacked memory, which NVIDIA says will well over triple (almost quadruple) the bandwidth, from 288 to 1000 around a TB/sec. Additionally, this fix to the off-package GDDR5 is set to offer around 4x the energy efficiency by making the voltage regulators and compute close neighbors.

“GPUs have 288 GB/s of bandwidth already, which is many times that of the CPU—the very reason why GPUs contribute so much to parallel computation,” said Huang. “Of course we would love to have many times more. But the challenge is, the GPU already has a lot of pins; it’s already the biggest chip in the world. The interface is already very wide. How do you solve this when going wider would make the package enormous and making the signaling go faster would push down energy efficiency and we know we’re power limited in almost every application we’re pursing?”

Click here to view photos from the NVIDIA GPU Technology Conference 2014
Click here to view photos from the NVIDIA GPU Technology Conference 2014
Huang answered his own questions by introducing Pascal, which is the size of an iPhone (around 1/3 the size of a PCIe card), which will sport the 3D memory and first-generation of NVLink. What’s rather interesting about the outlook for Pascal is that Huang didn’t talk about it in terms of form factors. He referred to it simply as a “module”, meaning that while servers are a natural home, NVIDIA wants to shop around for other places to place it.

During the keynote the emphasis was on various modes of mobility and access—from cloud-delivered services, self-driving cars with modular units in the trunk, hints at ultrasound and other medical devices being suitable hosts and more. In short, as we wait for NVIDIA to roll out Volta, Maxwell and eventually Pascal, could be making the rounds outside of the box.

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

Jack Dongarra on SC21, the Top500 and His Retirement Plans

November 29, 2021

HPCwire's Managing Editor sits down with Jack Dongarra, Top500 co-founder and Distinguished Professor at the University of Tennessee, during SC21 in St. Louis to discuss the 2021 Top500 list, the outlook for global exascale computing, and what exactly is going on in that Viking helmet photo. Read more…

SC21: Larry Smarr on The Rise of Supernetwork Data Intensive Computing

November 26, 2021

Larry Smarr, founding director of Calit2 (now Distinguished Professor Emeritus at the University of California San Diego) and the first director of NCSA, is one of the seminal figures in the U.S. supercomputing community. What began as a personal drive, shared by others, to spur the creation of supercomputers in the U.S. for scientific use, later expanded into a... Read more…

Three Chinese Exascale Systems Detailed at SC21: Two Operational and One Delayed

November 24, 2021

Details about two previously rumored Chinese exascale systems came to light during last week’s SC21 proceedings. Asked about these systems during the Top500 media briefing on Monday, Nov. 15, list author and co-founder Jack Dongarra indicated he was aware of some very impressive results, but withheld comment when asked directly if he had... Read more…

SC21’s Student Cluster Competition Winners Announced

November 19, 2021

SC21 may have been the first major supercomputing conference to return to in-person activities, but not everything returned to the live menu: the Student Cluster Competition – held virtually at ISC 2020, SC20 and ISC 2021 – was again held virtually at SC21. Nevertheless, Students@SC Chair Jay Lofstead took the physical stage at SC21 on Thursday to announce the... Read more…

MLPerf Issues HPC 1.0 Benchmark Results Featuring Impressive Systems (Think Fugaku)

November 19, 2021

Earlier this week MLCommons issued results from its latest MLPerf HPC training benchmarking exercise. Unlike other MLPerf benchmarks, which mostly measure the training and inference performance of systems that are availa Read more…

AWS Solution Channel

Royalty-free stock illustration ID: 1616974732

Using the Slurm REST API to integrate with distributed architectures on AWS

The Slurm Workload Manager by SchedMD is a popular HPC scheduler and is supported by AWS ParallelCluster, an elastic HPC cluster management service offered by AWS. Read more…

Gordon Bell Special Prize Goes to World-Shaping COVID Droplet Work

November 18, 2021

For the second (and, hopefully, final) year in a row, SC21 included a second major research award alongside the ACM 2021 Gordon Bell Prize: the Gordon Bell Special Prize for High Performance Computing-Based COVID-19 Research. Last year, the first iteration of this award went to simulations of the SARS-CoV-2 spike protein; this year, the prize went... Read more…

Jack Dongarra on SC21, the Top500 and His Retirement Plans

November 29, 2021

HPCwire's Managing Editor sits down with Jack Dongarra, Top500 co-founder and Distinguished Professor at the University of Tennessee, during SC21 in St. Louis to discuss the 2021 Top500 list, the outlook for global exascale computing, and what exactly is going on in that Viking helmet photo. Read more…

SC21: Larry Smarr on The Rise of Supernetwork Data Intensive Computing

November 26, 2021

Larry Smarr, founding director of Calit2 (now Distinguished Professor Emeritus at the University of California San Diego) and the first director of NCSA, is one of the seminal figures in the U.S. supercomputing community. What began as a personal drive, shared by others, to spur the creation of supercomputers in the U.S. for scientific use, later expanded into a... Read more…

Three Chinese Exascale Systems Detailed at SC21: Two Operational and One Delayed

November 24, 2021

Details about two previously rumored Chinese exascale systems came to light during last week’s SC21 proceedings. Asked about these systems during the Top500 media briefing on Monday, Nov. 15, list author and co-founder Jack Dongarra indicated he was aware of some very impressive results, but withheld comment when asked directly if he had... Read more…

SC21’s Student Cluster Competition Winners Announced

November 19, 2021

SC21 may have been the first major supercomputing conference to return to in-person activities, but not everything returned to the live menu: the Student Cluster Competition – held virtually at ISC 2020, SC20 and ISC 2021 – was again held virtually at SC21. Nevertheless, Students@SC Chair Jay Lofstead took the physical stage at SC21 on Thursday to announce the... Read more…

MLPerf Issues HPC 1.0 Benchmark Results Featuring Impressive Systems (Think Fugaku)

November 19, 2021

Earlier this week MLCommons issued results from its latest MLPerf HPC training benchmarking exercise. Unlike other MLPerf benchmarks, which mostly measure the t Read more…

Gordon Bell Special Prize Goes to World-Shaping COVID Droplet Work

November 18, 2021

For the second (and, hopefully, final) year in a row, SC21 included a second major research award alongside the ACM 2021 Gordon Bell Prize: the Gordon Bell Special Prize for High Performance Computing-Based COVID-19 Research. Last year, the first iteration of this award went to simulations of the SARS-CoV-2 spike protein; this year, the prize went... Read more…

2021 Gordon Bell Prize Goes to Exascale-Powered Quantum Supremacy Challenge

November 18, 2021

Today at the hybrid virtual/in-person SC21 conference, the organizers announced the winners of the 2021 ACM Gordon Bell Prize: a team of Chinese researchers leveraging the new exascale Sunway system to simulate quantum circuits. The Gordon Bell Prize, which comes with an award of $10,000 courtesy of HPC pioneer Gordon Bell, is awarded annually... Read more…

SC21 Keynote: Internet Pioneer Vint Cerf on Shakespeare, Chatbots, and Being Human

November 17, 2021

Unlike the deep technical dives of many SC keynotes, Internet pioneer Vint Cerf steered clear of the trenches and took leisurely stroll through a range of human-machine interactions, touching on ML’s growing capabilities while noting potholes to be avoided if possible. Cerf, of course, is co-designer with Bob Kahn of the TCP/IP protocols and architecture of the internet. He’s heralded... Read more…

IonQ Is First Quantum Startup to Go Public; Will It be First to Deliver Profits?

November 3, 2021

On October 1 of this year, IonQ became the first pure-play quantum computing start-up to go public. At this writing, the stock (NYSE: IONQ) was around $15 and its market capitalization was roughly $2.89 billion. Co-founder and chief scientist Chris Monroe says it was fun to have a few of the company’s roughly 100 employees travel to New York to ring the opening bell of the New York Stock... Read more…

Enter Dojo: Tesla Reveals Design for Modular Supercomputer & D1 Chip

August 20, 2021

Two months ago, Tesla revealed a massive GPU cluster that it said was “roughly the number five supercomputer in the world,” and which was just a precursor to Tesla’s real supercomputing moonshot: the long-rumored, little-detailed Dojo system. Read more…

Esperanto, Silicon in Hand, Champions the Efficiency of Its 1,092-Core RISC-V Chip

August 27, 2021

Esperanto Technologies made waves last December when it announced ET-SoC-1, a new RISC-V-based chip aimed at machine learning that packed nearly 1,100 cores onto a package small enough to fit six times over on a single PCIe card. Now, Esperanto is back, silicon in-hand and taking aim... Read more…

US Closes in on Exascale: Frontier Installation Is Underway

September 29, 2021

At the Advanced Scientific Computing Advisory Committee (ASCAC) meeting, held by Zoom this week (Sept. 29-30), it was revealed that the Frontier supercomputer is currently being installed at Oak Ridge National Laboratory in Oak Ridge, Tenn. The staff at the Oak Ridge Leadership... Read more…

AMD Launches Milan-X CPU with 3D V-Cache and Multichip Instinct MI200 GPU

November 8, 2021

At a virtual event this morning, AMD CEO Lisa Su unveiled the company’s latest and much-anticipated server products: the new Milan-X CPU, which leverages AMD’s new 3D V-Cache technology; and its new Instinct MI200 GPU, which provides up to 220 compute units across two Infinity Fabric-connected dies, delivering an astounding 47.9 peak double-precision teraflops. “We're in a high-performance computing megacycle, driven by the growing need to deploy additional compute performance... Read more…

Intel Reorgs HPC Group, Creates Two ‘Super Compute’ Groups

October 15, 2021

Following on changes made in June that moved Intel’s HPC unit out of the Data Platform Group and into the newly created Accelerated Computing Systems and Graphics (AXG) business unit, led by Raja Koduri, Intel is making further updates to the HPC group and announcing... Read more…

Intel Completes LLVM Adoption; Will End Updates to Classic C/C++ Compilers in Future

August 10, 2021

Intel reported in a blog this week that its adoption of the open source LLVM architecture for Intel’s C/C++ compiler is complete. The transition is part of In Read more…

Killer Instinct: AMD’s Multi-Chip MI200 GPU Readies for a Major Global Debut

October 21, 2021

AMD’s next-generation supercomputer GPU is on its way – and by all appearances, it’s about to make a name for itself. The AMD Radeon Instinct MI200 GPU (a successor to the MI100) will, over the next year, begin to power three massive systems on three continents: the United States’ exascale Frontier system; the European Union’s pre-exascale LUMI system; and Australia’s petascale Setonix system. Read more…

Leading Solution Providers

Contributors

Hot Chips: Here Come the DPUs and IPUs from Arm, Nvidia and Intel

August 25, 2021

The emergence of data processing units (DPU) and infrastructure processing units (IPU) as potentially important pieces in cloud and datacenter architectures was Read more…

D-Wave Embraces Gate-Based Quantum Computing; Charts Path Forward

October 21, 2021

Earlier this month D-Wave Systems, the quantum computing pioneer that has long championed quantum annealing-based quantum computing (and sometimes taken heat fo Read more…

Ahead of ‘Dojo,’ Tesla Reveals Its Massive Precursor Supercomputer

June 22, 2021

In spring 2019, Tesla made cryptic reference to a project called Dojo, a “super-powerful training computer” for video data processing. Then, in summer 2020, Tesla CEO Elon Musk tweeted: “Tesla is developing a [neural network] training computer... Read more…

HPE Wins $2B GreenLake HPC-as-a-Service Deal with NSA

September 1, 2021

In the heated, oft-contentious, government IT space, HPE has won a massive $2 billion contract to provide HPC and AI services to the United States’ National Security Agency (NSA). Following on the heels of the now-canceled $10 billion JEDI contract (reissued as JWCC) and a $10 billion... Read more…

The Latest MLPerf Inference Results: Nvidia GPUs Hold Sway but Here Come CPUs and Intel

September 22, 2021

The latest round of MLPerf inference benchmark (v 1.1) results was released today and Nvidia again dominated, sweeping the top spots in the closed (apples-to-ap Read more…

Quantum Computer Market Headed to $830M in 2024

September 13, 2021

What is one to make of the quantum computing market? Energized (lots of funding) but still chaotic and advancing in unpredictable ways (e.g. competing qubit tec Read more…

10nm, 7nm, 5nm…. Should the Chip Nanometer Metric Be Replaced?

June 1, 2020

The biggest cool factor in server chips is the nanometer. AMD beating Intel to a CPU built on a 7nm process node* – with 5nm and 3nm on the way – has been i Read more…

2021 Gordon Bell Prize Goes to Exascale-Powered Quantum Supremacy Challenge

November 18, 2021

Today at the hybrid virtual/in-person SC21 conference, the organizers announced the winners of the 2021 ACM Gordon Bell Prize: a team of Chinese researchers leveraging the new exascale Sunway system to simulate quantum circuits. The Gordon Bell Prize, which comes with an award of $10,000 courtesy of HPC pioneer Gordon Bell, is awarded annually... Read more…

  • arrow
  • Click Here for More Headlines
  • arrow
HPCwire