Emerging System Sets Stage for Exascale Science

By Nicole Hemsoth

April 29, 2014

Today we welcome a new large-scale system into the high performance computing fold with the formal announcement of Cori, a new supercomputer set to be installed at NERSC in the mid-2016 timeframe. Known in its RFP stages as NERSC-8, the new machine will sport over 9,300 nodes, featuring the next-generation Knights Landing architecture housed within a Cray XC environment.

In the original request for vendor input on the system, NERSC said they required a new HPC environment to support the broad array of scientific projects that run at the center. This system had to “provide a significant upgrade in computational capabilities, with at least a ten-times increase in sustained performance over the NERSC-6 Hopper system on a set of representative benchmarks.” With 3 teraflops of double-precision peak performance per node expected from the Knight’s Landing-based Cray Cori machine, there is set to be a clear 10x (or more) improvement. The addition of over 400 GbS of IO bandwidth and 28 petabytes of disk make this quite a powerhouse—but again, the real emphasis is not on peak or capability, it’s on true application performance and showing a path to using new architectures and approaches for next generation science.

What’s interesting about the new supercomputer is that it’s been designed as a proving ground of sorts for some of the key barriers on the exascale computing front, including resiliency, programming to exploit massive levels of parallelism, and support for data-intensive scientific computing applications in software, hardware, memory and storage systems. Key to exploring solutions around these barriers are the Knight’s Landing manycore, self-hosted architecture and more novel approaches to extending reliability and performance with flash memory. The point of the system, as NERSC folks we talked to leading up to the announcement repeated constantly, has been to serve the highly diverse workloads of over 5,000 users that will make use of the system…not to appeal to compute-based benchmarks like LINPACK, although that sentiment is not new these days.

While we have often heard variables on the eventual core count of the Knight’s Landing processors set to appear in this system, Katie Antypas, head of NERSC’s Services Department, said there will be “more than sixty cores” on each of the cards.  But as Antypas repeated several times during our conversation about Cori, the real appeal has a lot less to do with compute horsepower than it does real application requirements. The access to high-bandwidth on-package memory  with the next-generation Intel part is the real appeal, she noted. “This is critical for our workloads because we’ve found that most of our applications aren’t limited by compute—they’re held back because of memory bandwidth.” While performance and efficiency are key, “for users, having this self-hosted architecture means there is no need to worry about moving data on and off a coprocessor.”

Antypas notes that even with a familiar programming environment and lessened emphasis on the challenges of data movement inside the node, there’s still a big optimization challenge ahead. “We know it will be a challenge for some of our users since they will need to find more parallelism in order to port their applications to a new architecture.” Still, she says, “we knew that for the long term to satisfy our mission to deliver more computing capability for our users, we needed to go down the manycore and more efficient route.”

There’s another unique element that the team will watch play out in advance of the wave of exascale systems eventually. The contract noted an option for burst buffer technology. In essence, this a layer of NVRAM that sits between the memory and disk to accelerate IO in the system. This is a core part of what Nick Wright, Advanced Technologies Group lead at NERSC will be watching once it’s up and running, both in terms of how it’s able to sate some key reliability concerns and to explore how it can enhance the increasingly important IOPS capabilities of the machine.

Wright says his team is looking at the burst buffer option for data-intensive computing as well as for addressing traditional HPC resiliency because of its checkpoint restart capabilities. “For data-intensive applications, one of the things about flash memory is that it has significantly higher IOPS than regular spinning disk—we’re seeing that many of the data-intensive apps are IOPS bound as well as general IO bandwidth bound, so we want to explore what new capabilities in scientific computing we can enable.”

For this piece of the system, Cray will be working with the software side but they’re still evaluating who the vendor will be for the hardware piece of the burst buffer. Wright says they want to integrate as much commodity technology as possible, but there’s benefit in waiting. The machine isn’t due for delivery for a while so that lets them ride out the drop in flash prices for a bit until they’re actually ready to pounce, instead of investing now in technology they’re not ready to use yet.

As Antypas said, “flash delivers bandwidth more cost effectively, so to give users the bandwidth they need, folks like us at NERSC have been buying really large parallel file systems. But the price of flash has come to the point that it looks much more promising for our supers. It can be a significant increase in bandwidth, and accelerating IO and spending more time computing is right what we want to do.”

Antypas and Wright agree that the burst buffer, both as a checkpoint and restarting merchanism to make rollbacks and checkpointing far faster and more efficient, as well as for driving data-intensive science, is something that they expect to see in exascale systems. They hope to share lessons learned for future systems—but for now are focusing on evolving applications according to the manycore architecture at hand, which represents a good view of the future.

As Sudip Dosanjh, Director of the National Energy Research Scientific Computing Center at Lawrence Berkeley National Laboratory summarized, “Cori will provide a significant increase in capability for our users and will provide a platform for transitioning our very broad user community to many core architectures. We will collaborate with Cray to ensure that Cori meets the computational and data needs of DOE’s science community.”

“We are thrilled to work with Cray in bringing the next generation of highly parallel supercomputers to market based on the Intel Xeon Phi processor – codenamed Knights Landing,” said Charles Wuischpard, Intel’s Vice President, Data Center Group and General Manager, Workstation and High Performance Computing. “Working closely with Cray, we will deploy the Many Integrated Core (MIC) architecture on the next generation Cray XC supercomputer, delivering over 3 teraflops of performance per single socket node to power a wide set of applications and taking an important and viable step towards Exascale.”

For some notable reads, check out the benchmarks here—congrats to our friends at NERSC and their new addition!

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

SC Bids Farewell to Denver, Heads to Dallas for 30th

November 17, 2017

After a jam-packed four-day expo and intensive six-day technical program, SC17 has wrapped up another successful event that brought together nearly 13,000 visitors to the Colorado Convention Center in Denver for the larg Read more…

By Tiffany Trader

SC17 Keynote – HPC Powers SKA Efforts to Peer Deep into the Cosmos

November 17, 2017

This week’s SC17 keynote – Life, the Universe and Computing: The Story of the SKA Telescope – was a powerful pitch for the potential of Big Science projects that also showcased the foundational role of high performance computing in modern science. It was also visually stunning. Read more…

By John Russell

How Cities Use HPC at the Edge to Get Smarter

November 17, 2017

Cities are sensoring up, collecting vast troves of data that they’re running through predictive models and using the insights to solve problems that, in some cases, city managers didn’t even know existed. Speaking Read more…

By Doug Black

HPE Extreme Performance Solutions

Harness Scalable Petabyte Storage with HPE Apollo 4510 and HPE StoreEver

As a growing number of connected devices challenges IT departments to rapidly collect, manage, and store troves of data, organizations must adopt a new generation of IT to help them operate quickly and intelligently. Read more…

SC17 Student Cluster Competition Configurations: Fewer Nodes, Way More Accelerators

November 16, 2017

The final configurations for each of the SC17 “Donnybrook in Denver” Student Cluster Competition have been released. Fortunately, each team received their equipment shipments on time and undamaged, so the teams are r Read more…

By Dan Olds

SC Bids Farewell to Denver, Heads to Dallas for 30th

November 17, 2017

After a jam-packed four-day expo and intensive six-day technical program, SC17 has wrapped up another successful event that brought together nearly 13,000 visit Read more…

By Tiffany Trader

SC17 Keynote – HPC Powers SKA Efforts to Peer Deep into the Cosmos

November 17, 2017

This week’s SC17 keynote – Life, the Universe and Computing: The Story of the SKA Telescope – was a powerful pitch for the potential of Big Science projects that also showcased the foundational role of high performance computing in modern science. It was also visually stunning. Read more…

By John Russell

How Cities Use HPC at the Edge to Get Smarter

November 17, 2017

Cities are sensoring up, collecting vast troves of data that they’re running through predictive models and using the insights to solve problems that, in some Read more…

By Doug Black

Student Cluster LINPACK Record Shattered! More LINs Packed Than Ever before!

November 16, 2017

Nanyang Technological University, the pride of Singapore, utterly destroyed the Student Cluster Competition LINPACK record by posting a score of 51.77 TFlop/s a Read more…

By Dan Olds

Hyperion Market Update: ‘Decent’ Growth Led by HPE; AI Transparency a Risk Issue

November 15, 2017

The HPC market update from Hyperion Research (formerly IDC) at the annual SC conference is a business and social “must,” and this year’s presentation at S Read more…

By Doug Black

Nvidia Focuses Its Cloud Containers on HPC Applications

November 14, 2017

Having migrated its top-of-the-line datacenter GPU to the largest cloud vendors, Nvidia is touting its Volta architecture for a range of scientific computing ta Read more…

By George Leopold

HPE Launches ARM-based Apollo System for HPC, AI

November 14, 2017

HPE doubled down on its memory-driven computing vision while expanding its processor portfolio with the announcement yesterday of the company’s first ARM-base Read more…

By Doug Black

OpenACC Shines in Global Climate/Weather Codes

November 14, 2017

OpenACC, the directive-based parallel programming model used mostly for porting codes to GPUs for use on heterogeneous systems, came to SC17 touting impressive Read more…

By John Russell

US Coalesces Plans for First Exascale Supercomputer: Aurora in 2021

September 27, 2017

At the Advanced Scientific Computing Advisory Committee (ASCAC) meeting, in Arlington, Va., yesterday (Sept. 26), it was revealed that the "Aurora" supercompute Read more…

By Tiffany Trader

NERSC Scales Scientific Deep Learning to 15 Petaflops

August 28, 2017

A collaborative effort between Intel, NERSC and Stanford has delivered the first 15-petaflops deep learning software running on HPC platforms and is, according Read more…

By Rob Farber

Oracle Layoffs Reportedly Hit SPARC and Solaris Hard

September 7, 2017

Oracle’s latest layoffs have many wondering if this is the end of the line for the SPARC processor and Solaris OS development. As reported by multiple sources Read more…

By John Russell

Nvidia Responds to Google TPU Benchmarking

April 10, 2017

Nvidia highlights strengths of its newest GPU silicon in response to Google's report on the performance and energy advantages of its custom tensor processor. Read more…

By Tiffany Trader

AMD Showcases Growing Portfolio of EPYC and Radeon-based Systems at SC17

November 13, 2017

AMD’s charge back into HPC and the datacenter is on full display at SC17. Having launched the EPYC processor line in June along with its MI25 GPU the focus he Read more…

By John Russell

Google Releases Deeplearn.js to Further Democratize Machine Learning

August 17, 2017

Spreading the use of machine learning tools is one of the goals of Google’s PAIR (People + AI Research) initiative, which was introduced in early July. Last w Read more…

By John Russell

GlobalFoundries Puts Wind in AMD’s Sails with 12nm FinFET

September 24, 2017

From its annual tech conference last week (Sept. 20), where GlobalFoundries welcomed more than 600 semiconductor professionals (reaching the Santa Clara venue Read more…

By Tiffany Trader

Amazon Debuts New AMD-based GPU Instances for Graphics Acceleration

September 12, 2017

Last week Amazon Web Services (AWS) streaming service, AppStream 2.0, introduced a new GPU instance called Graphics Design intended to accelerate graphics. The Read more…

By John Russell

Leading Solution Providers

EU Funds 20 Million Euro ARM+FPGA Exascale Project

September 7, 2017

At the Barcelona Supercomputer Centre on Wednesday (Sept. 6), 16 partners gathered to launch the EuroEXA project, which invests €20 million over three-and-a-half years into exascale-focused research and development. Led by the Horizon 2020 program, EuroEXA picks up the banner of a triad of partner projects — ExaNeSt, EcoScale and ExaNoDe — building on their work... Read more…

By Tiffany Trader

Delays, Smoke, Records & Markets – A Candid Conversation with Cray CEO Peter Ungaro

October 5, 2017

Earlier this month, Tom Tabor, publisher of HPCwire and I had a very personal conversation with Cray CEO Peter Ungaro. Cray has been on something of a Cinderell Read more…

By Tiffany Trader & Tom Tabor

Reinders: “AVX-512 May Be a Hidden Gem” in Intel Xeon Scalable Processors

June 29, 2017

Imagine if we could use vector processing on something other than just floating point problems.  Today, GPUs and CPUs work tirelessly to accelerate algorithms Read more…

By James Reinders

Cray Moves to Acquire the Seagate ClusterStor Line

July 28, 2017

This week Cray announced that it is picking up Seagate's ClusterStor HPC storage array business for an undisclosed sum. "In short we're effectively transitioning the bulk of the ClusterStor product line to Cray," said CEO Peter Ungaro. Read more…

By Tiffany Trader

Intel Launches Software Tools to Ease FPGA Programming

September 5, 2017

Field Programmable Gate Arrays (FPGAs) have a reputation for being difficult to program, requiring expertise in specialty languages, like Verilog or VHDL. Easin Read more…

By Tiffany Trader

HPC Chips – A Veritable Smorgasbord?

October 10, 2017

For the first time since AMD's ill-fated launch of Bulldozer the answer to the question, 'Which CPU will be in my next HPC system?' doesn't have to be 'Whichever variety of Intel Xeon E5 they are selling when we procure'. Read more…

By Dairsie Latimer

IBM Advances Web-based Quantum Programming

September 5, 2017

IBM Research is pairing its Jupyter-based Data Science Experience notebook environment with its cloud-based quantum computer, IBM Q, in hopes of encouraging a new class of entrepreneurial user to solve intractable problems that even exceed the capabilities of the best AI systems. Read more…

By Alex Woodie

How ‘Knights Mill’ Gets Its Deep Learning Flops

June 22, 2017

Intel, the subject of much speculation regarding the delayed, rewritten or potentially canceled “Aurora” contract (the Argonne Lab part of the CORAL “ Read more…

By Tiffany Trader

  • arrow
  • Click Here for More Headlines
  • arrow
Share This