Emerging System Sets Stage for Exascale Science

By Nicole Hemsoth

April 29, 2014

Today we welcome a new large-scale system into the high performance computing fold with the formal announcement of Cori, a new supercomputer set to be installed at NERSC in the mid-2016 timeframe. Known in its RFP stages as NERSC-8, the new machine will sport over 9,300 nodes, featuring the next-generation Knights Landing architecture housed within a Cray XC environment.

In the original request for vendor input on the system, NERSC said they required a new HPC environment to support the broad array of scientific projects that run at the center. This system had to “provide a significant upgrade in computational capabilities, with at least a ten-times increase in sustained performance over the NERSC-6 Hopper system on a set of representative benchmarks.” With 3 teraflops of double-precision peak performance per node expected from the Knight’s Landing-based Cray Cori machine, there is set to be a clear 10x (or more) improvement. The addition of over 400 GbS of IO bandwidth and 28 petabytes of disk make this quite a powerhouse—but again, the real emphasis is not on peak or capability, it’s on true application performance and showing a path to using new architectures and approaches for next generation science.

What’s interesting about the new supercomputer is that it’s been designed as a proving ground of sorts for some of the key barriers on the exascale computing front, including resiliency, programming to exploit massive levels of parallelism, and support for data-intensive scientific computing applications in software, hardware, memory and storage systems. Key to exploring solutions around these barriers are the Knight’s Landing manycore, self-hosted architecture and more novel approaches to extending reliability and performance with flash memory. The point of the system, as NERSC folks we talked to leading up to the announcement repeated constantly, has been to serve the highly diverse workloads of over 5,000 users that will make use of the system…not to appeal to compute-based benchmarks like LINPACK, although that sentiment is not new these days.

While we have often heard variables on the eventual core count of the Knight’s Landing processors set to appear in this system, Katie Antypas, head of NERSC’s Services Department, said there will be “more than sixty cores” on each of the cards.  But as Antypas repeated several times during our conversation about Cori, the real appeal has a lot less to do with compute horsepower than it does real application requirements. The access to high-bandwidth on-package memory  with the next-generation Intel part is the real appeal, she noted. “This is critical for our workloads because we’ve found that most of our applications aren’t limited by compute—they’re held back because of memory bandwidth.” While performance and efficiency are key, “for users, having this self-hosted architecture means there is no need to worry about moving data on and off a coprocessor.”

Antypas notes that even with a familiar programming environment and lessened emphasis on the challenges of data movement inside the node, there’s still a big optimization challenge ahead. “We know it will be a challenge for some of our users since they will need to find more parallelism in order to port their applications to a new architecture.” Still, she says, “we knew that for the long term to satisfy our mission to deliver more computing capability for our users, we needed to go down the manycore and more efficient route.”

There’s another unique element that the team will watch play out in advance of the wave of exascale systems eventually. The contract noted an option for burst buffer technology. In essence, this a layer of NVRAM that sits between the memory and disk to accelerate IO in the system. This is a core part of what Nick Wright, Advanced Technologies Group lead at NERSC will be watching once it’s up and running, both in terms of how it’s able to sate some key reliability concerns and to explore how it can enhance the increasingly important IOPS capabilities of the machine.

Wright says his team is looking at the burst buffer option for data-intensive computing as well as for addressing traditional HPC resiliency because of its checkpoint restart capabilities. “For data-intensive applications, one of the things about flash memory is that it has significantly higher IOPS than regular spinning disk—we’re seeing that many of the data-intensive apps are IOPS bound as well as general IO bandwidth bound, so we want to explore what new capabilities in scientific computing we can enable.”

For this piece of the system, Cray will be working with the software side but they’re still evaluating who the vendor will be for the hardware piece of the burst buffer. Wright says they want to integrate as much commodity technology as possible, but there’s benefit in waiting. The machine isn’t due for delivery for a while so that lets them ride out the drop in flash prices for a bit until they’re actually ready to pounce, instead of investing now in technology they’re not ready to use yet.

As Antypas said, “flash delivers bandwidth more cost effectively, so to give users the bandwidth they need, folks like us at NERSC have been buying really large parallel file systems. But the price of flash has come to the point that it looks much more promising for our supers. It can be a significant increase in bandwidth, and accelerating IO and spending more time computing is right what we want to do.”

Antypas and Wright agree that the burst buffer, both as a checkpoint and restarting merchanism to make rollbacks and checkpointing far faster and more efficient, as well as for driving data-intensive science, is something that they expect to see in exascale systems. They hope to share lessons learned for future systems—but for now are focusing on evolving applications according to the manycore architecture at hand, which represents a good view of the future.

As Sudip Dosanjh, Director of the National Energy Research Scientific Computing Center at Lawrence Berkeley National Laboratory summarized, “Cori will provide a significant increase in capability for our users and will provide a platform for transitioning our very broad user community to many core architectures. We will collaborate with Cray to ensure that Cori meets the computational and data needs of DOE’s science community.”

“We are thrilled to work with Cray in bringing the next generation of highly parallel supercomputers to market based on the Intel Xeon Phi processor – codenamed Knights Landing,” said Charles Wuischpard, Intel’s Vice President, Data Center Group and General Manager, Workstation and High Performance Computing. “Working closely with Cray, we will deploy the Many Integrated Core (MIC) architecture on the next generation Cray XC supercomputer, delivering over 3 teraflops of performance per single socket node to power a wide set of applications and taking an important and viable step towards Exascale.”

For some notable reads, check out the benchmarks here—congrats to our friends at NERSC and their new addition!

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

Machine Learning at HPC User Forum: Drilling into Specific Use Cases

September 22, 2017

The 66th HPC User Forum held September 5-7, in Milwaukee, Wisconsin, at the elegant and historic Pfister Hotel, highlighting the 1893 Victorian décor and art of “The Grand Hotel Of The West,” contrasted nicely with Read more…

By Arno Kolster

Google Cloud Makes Good on Promise to Add Nvidia P100 GPUs

September 21, 2017

Google has taken down the notice on its cloud platform website that says Nvidia Tesla P100s are “coming soon.” That's because the search giant has announced the beta launch of the high-end P100 Nvidia Tesla GPUs on t Read more…

By George Leopold

Cray Wins $48M Supercomputer Contract from KISTI

September 21, 2017

It was a good day for Cray which won a $48 million contract from the Korea Institute of Science and Technology Information (KISTI) for a 128-rack CS500 cluster supercomputer. The new system, equipped with Intel Xeon Scal Read more…

By John Russell

HPE Extreme Performance Solutions

HPE Prepares Customers for Success with the HPC Software Portfolio

High performance computing (HPC) software is key to harnessing the full power of HPC environments. Development and management tools enable IT departments to streamline installation and maintenance of their systems as well as create, optimize, and run their HPC applications. Read more…

Adolfy Hoisie to Lead Brookhaven’s Computing for National Security Effort

September 21, 2017

Brookhaven National Laboratory announced today that Adolfy Hoisie will chair its newly formed Computing for National Security department, which is part of Brookhaven’s new Computational Science Initiative (CSI). Read more…

By John Russell

Machine Learning at HPC User Forum: Drilling into Specific Use Cases

September 22, 2017

The 66th HPC User Forum held September 5-7, in Milwaukee, Wisconsin, at the elegant and historic Pfister Hotel, highlighting the 1893 Victorian décor and art o Read more…

By Arno Kolster

Stanford University and UberCloud Achieve Breakthrough in Living Heart Simulations

September 21, 2017

Cardiac arrhythmia can be an undesirable and potentially lethal side effect of drugs. During this condition, the electrical activity of the heart turns chaotic, Read more…

By Wolfgang Gentzsch, UberCloud, and Francisco Sahli, Stanford University

PNNL’s Center for Advanced Tech Evaluation Seeks Wider HPC Community Ties

September 21, 2017

Two years ago the Department of Energy established the Center for Advanced Technology Evaluation (CENATE) at Pacific Northwest National Laboratory (PNNL). CENAT Read more…

By John Russell

Exascale Computing Project Names Doug Kothe as Director

September 20, 2017

The Department of Energy’s Exascale Computing Project (ECP) has named Doug Kothe as its new director effective October 1. He replaces Paul Messina, who is stepping down after two years to return to Argonne National Laboratory. Kothe is a 32-year veteran of DOE’s National Laboratory System. Read more…

Takeaways from the Milwaukee HPC User Forum

September 19, 2017

Milwaukee’s elegant Pfister Hotel hosted approximately 100 attendees for the 66th HPC User Forum (September 5-7, 2017). In the original home city of Pabst Blu Read more…

By Merle Giles

Kathy Yelick Charts the Promise and Progress of Exascale Science

September 15, 2017

On Friday, Sept. 8, Kathy Yelick of Lawrence Berkeley National Laboratory and the University of California, Berkeley, delivered the keynote address on “Breakthrough Science at the Exascale” at the ACM Europe Conference in Barcelona. In conjunction with her presentation, Yelick agreed to a short Q&A discussion with HPCwire. Read more…

By Tiffany Trader

DARPA Pledges Another $300 Million for Post-Moore’s Readiness

September 14, 2017

The Defense Advanced Research Projects Agency (DARPA) launched a giant funding effort to ensure the United States can sustain the pace of electronic innovation vital to both a flourishing economy and a secure military. Under the banner of the Electronics Resurgence Initiative (ERI), some $500-$800 million will be invested in post-Moore’s Law technologies. Read more…

By Tiffany Trader

IBM Breaks Ground for Complex Quantum Chemistry

September 14, 2017

IBM has reported the use of a novel algorithm to simulate BeH2 (beryllium-hydride) on a quantum computer. This is the largest molecule so far simulated on a quantum computer. The technique, which used six qubits of a seven-qubit system, is an important step forward and may suggest an approach to simulating ever larger molecules. Read more…

By John Russell

How ‘Knights Mill’ Gets Its Deep Learning Flops

June 22, 2017

Intel, the subject of much speculation regarding the delayed, rewritten or potentially canceled “Aurora” contract (the Argonne Lab part of the CORAL “ Read more…

By Tiffany Trader

Reinders: “AVX-512 May Be a Hidden Gem” in Intel Xeon Scalable Processors

June 29, 2017

Imagine if we could use vector processing on something other than just floating point problems.  Today, GPUs and CPUs work tirelessly to accelerate algorithms Read more…

By James Reinders

NERSC Scales Scientific Deep Learning to 15 Petaflops

August 28, 2017

A collaborative effort between Intel, NERSC and Stanford has delivered the first 15-petaflops deep learning software running on HPC platforms and is, according Read more…

By Rob Farber

Oracle Layoffs Reportedly Hit SPARC and Solaris Hard

September 7, 2017

Oracle’s latest layoffs have many wondering if this is the end of the line for the SPARC processor and Solaris OS development. As reported by multiple sources Read more…

By John Russell

Six Exascale PathForward Vendors Selected; DoE Providing $258M

June 15, 2017

The much-anticipated PathForward awards for hardware R&D in support of the Exascale Computing Project were announced today with six vendors selected – AMD Read more…

By John Russell

Top500 Results: Latest List Trends and What’s in Store

June 19, 2017

Greetings from Frankfurt and the 2017 International Supercomputing Conference where the latest Top500 list has just been revealed. Although there were no major Read more…

By Tiffany Trader

IBM Clears Path to 5nm with Silicon Nanosheets

June 5, 2017

Two years since announcing the industry’s first 7nm node test chip, IBM and its research alliance partners GlobalFoundries and Samsung have developed a proces Read more…

By Tiffany Trader

Nvidia Responds to Google TPU Benchmarking

April 10, 2017

Nvidia highlights strengths of its newest GPU silicon in response to Google's report on the performance and energy advantages of its custom tensor processor. Read more…

By Tiffany Trader

Leading Solution Providers

Graphcore Readies Launch of 16nm Colossus-IPU Chip

July 20, 2017

A second $30 million funding round for U.K. AI chip developer Graphcore sets up the company to go to market with its “intelligent processing unit” (IPU) in Read more…

By Tiffany Trader

Google Releases Deeplearn.js to Further Democratize Machine Learning

August 17, 2017

Spreading the use of machine learning tools is one of the goals of Google’s PAIR (People + AI Research) initiative, which was introduced in early July. Last w Read more…

By John Russell

Russian Researchers Claim First Quantum-Safe Blockchain

May 25, 2017

The Russian Quantum Center today announced it has overcome the threat of quantum cryptography by creating the first quantum-safe blockchain, securing cryptocurrencies like Bitcoin, along with classified government communications and other sensitive digital transfers. Read more…

By Doug Black

Google Debuts TPU v2 and will Add to Google Cloud

May 25, 2017

Not long after stirring attention in the deep learning/AI community by revealing the details of its Tensor Processing Unit (TPU), Google last week announced the Read more…

By John Russell

EU Funds 20 Million Euro ARM+FPGA Exascale Project

September 7, 2017

At the Barcelona Supercomputer Centre on Wednesday (Sept. 6), 16 partners gathered to launch the EuroEXA project, which invests €20 million over three-and-a-half years into exascale-focused research and development. Led by the Horizon 2020 program, EuroEXA picks up the banner of a triad of partner projects — ExaNeSt, EcoScale and ExaNoDe — building on their work... Read more…

By Tiffany Trader

Amazon Debuts New AMD-based GPU Instances for Graphics Acceleration

September 12, 2017

Last week Amazon Web Services (AWS) streaming service, AppStream 2.0, introduced a new GPU instance called Graphics Design intended to accelerate graphics. The Read more…

By John Russell

Cray Moves to Acquire the Seagate ClusterStor Line

July 28, 2017

This week Cray announced that it is picking up Seagate's ClusterStor HPC storage array business for an undisclosed sum. "In short we're effectively transitioning the bulk of the ClusterStor product line to Cray," said CEO Peter Ungaro. Read more…

By Tiffany Trader

GlobalFoundries: 7nm Chips Coming in 2018, EUV in 2019

June 13, 2017

GlobalFoundries has formally announced that its 7nm technology is ready for customer engagement with product tape outs expected for the first half of 2018. The Read more…

By Tiffany Trader

  • arrow
  • Click Here for More Headlines
  • arrow
Share This