Los Alamos Lead Shares ‘Trinity’ Feeds and Speeds

By Nicole Hemsoth

July 10, 2014

We’ve been anticipating news around the Trinity supercomputer for some time now and today were graced with the news that Cray will be supplying the machine in two phases with the final phase being complete in 2016. For the original background, the first run of the story can be found here.

Since that time this morning, we were able to have an in-depth discussion with one of the key thinkers at the heart of the procurement, Los Alamos National Labs’ HPC division leader, Gary Grider. His foundational work on burst buffers (a term he coined) features prominently in the other half of the procurement, the NERSC “Cori” system, but he’s also been instrumental in making system-level choices for the NNSA’s mission-critical Trinity supercomputer, along with a great deal of assistance from project partners at Sandia.

Grider told us the team at Los Alamos is already busy installing the extra power and cooling needed to ready space inside the existing Strategic Computing Complex at the lab with the 45,000 square feet of space for the new system. The approximately 270 next-generation Cray XC racks won’t occupy that entire space, says Grider, but the 10,000 square feet it needs will be prepared with the warm water cooling infrastructure needed to keep the Haswell and Knights Landing-based nodes cool, while feeding recycled water that isn’t in the racks out into protected wetlands—thus offsetting some of the concerns about the 8-10 MW that the new super will likely consume. In the bigger picture, however, Los Alamos is thinking ahead—the facility itself is preparing to handle far more in terms of power and cooling with the capability of 30 MW in sight.

We weren’t able to tell this morning how large the machine might be, but started piecing things together with some information that’s available. We know that the next-generation Haswell core count will fall somewhere in the 14-18 range (perhaps up to 24—we’ll find this out in upcoming Intel announcements, probably this quarter) and with the additional Knights Landing chips, which will sport on-package memory and anywhere between 60-72 cores, according to the data we have available. In the end, Grider confirmed that the system will (like way far) exceed the original performance targets of 30 petaflops, but he’s not sure how far over the mark it will go for the machine. There’s some speculative math coming your way soon on this…but even if half the machine is just the Xeon…whew.

As we noted earlier today, we’ll do the math once the most recent Haswell core counts and expected performance/thermals come out soon—and add it to whatever Intel cares to share later this year about the future performance of its self-hosted Knights Landing part.

For those who keep supercomputing score (and Grider isn’t one of them—he doesn’t care about the FLOPS, he cares about getting 6x-8x the performance of their workhouse “Cielo” machine) recall that this would put the 2015-2016 NNSA supercomputer just around the existing #1 system in the world for 2 years running—China’s Tianhe-2. No small feat, but Grider says that they’re not planning LINPACK unless the vendors ask them to. And if Cray thought that spike in their stock price was attractive today, having twice a year news around another top super couldn’t hurt.

The two phases of the project mean that the first cores that will hit the floor will be the Haswells because the facility cannot wait for the Knights Landing to come into play. He says that for the other side of the procurement at NERSC, they had more flexibility in waiting on the chips because they have enough capacity to keep the Office of Science machines and researchers fed. The problem at the NNSA, however, is that they need more computing power immediately. They’re going to complete an install of the first set of Haswell-based machines in the summer of 2015—but the delay is just facilities-related. They need to get their power and cooling infrastructure secured before these can go in, he said, stressing that there are no delays on Intel’s part expected for the first component.

The precise configuration of the nodes in the Trinity machine have not been divulged, but it looks like there will be compute nodes with multiple Haswell Xeon E5 v3 processors on them as well as compute nodes that have multiple Knights Landing Xeon Phi processors on them. All of these devices will be connected using the Aries XC interconnect in its dragonfly topology.

It is not clear exactly how the processors will link to the Aries interconnect, but the current Aries chip is a 48-port router that has four PCI-Express 3.0 lanes linking to four two-socket Xeon nodes. The Aries chip also has three different ranks of connectivity: Rank 1 goes into the backplane, Rank 2 is a copper network for linking six XC enclosures to each other, and Rank 3 is an optical network that links multiple rack pairs to each other. Each server node has four two-socket servers and Aries interconnect in the current design. Conceptually, you could put Xeon E5s and Xeon Phis on the same server form factor. The important thing is that the Aries interconnect allows all nodes in the system to talk to one another. The system has what Cray calls adaptive routing, making use of multiple routes in the network to get around congestion, and that implies that the system can start out with Xeon processors and have Xeon Phi chips added later with relative ease.

One little note about the architectural choice goes back to an actual lack of choice. Grider says he’s been watching OpenPower efforts carefully, but they’re mission-driven at the NNSA and need the power and bandwidth now. The OpenPower roadmap, while presenting some attractive features, was too long to consider.

Discrete GPUs were not an option for the same reasons, said Grider, noting, “we probably would have considered this as an option if there was a self-hosted GPU of some kind or higher bandwidth than a PCI bus. Again, if you look at the time we were making these decisions and the chips avail in the timeframe, you’ll see that there’s really nothing else out there right now.”

While the architectural choice is already being questioned by some as being more conservative than expected, there are a few things to keep in mind. Unlike open science centers (including NERSC) the application demands are limited in terms of scope. Grider says there are less than a dozen codes set to run on the monster, but these have been refined and blessed over the course of many years. We don’t mess around when it comes to our nuclear facilities. This means retooling codes to fit into architectural boxes is impractical and further, that they have a very defined sense of exactly what they need. The choices for architecture, while very conservative, were the only choices.

But it’s not like there’s nothing interesting happening here. For instance, Grider, the originator of the burst buffer term and early research, said that they’re going to be seeking as much performance out of their flash array as possible—using the burst buffer technology for the first time on a large-scale machine in 2015 to see how it adds to their reliability and 90% utilization goals. And from a memory perspective, it’s nothing to sneeze at either—with 2-3 petabytes of main memory, that 7 petabyte flash gear to support the burst buffer, and 82 petabytes of disk, it’s quite the powerhouse overall—and even conservative for a burst buffer until they see exactly how Cray’s Tiered Storage stuff works in action.

“The burst buffer might be in the 5-7 TB/sec and the disk system is 1-2 TB/sec. The models show that you could sustain the 90% goal with less disk bandwidth, more like 10x less than the burst buffer BW instead of the 4-5x on this machine. This was a deliberate choice because of the immaturity of the burst buffer solution space. This is the first burst buffer solution being deployed and it is a pretty large scale deployment as well, so there is reason to be a little conservative. If we had complete confidence in the burst buffer solutions at this scale, we could have saved money by buying less disk BW. Future machines can be more aggressive in this area,” said Grider.

But there are risks, even with a conservative architecture. When asked what he worries about most in terms of implementation and early use nitty-gritty, Grider said there is concern that the architecture takes a turn from the heterogeneous approach where they had a strong integer machine and a strong processor (as with Roadrunner’s AMDs) where the network was attached.

“Since Knights Landing is such a flat architecture, where it’s just a bunch of equivalent-sized processors that are smaller and weaker whereas for hot processes you want a stronger processor, we’re going to have to do some thinking,” he said. In the next month, Grider added they’ll be pulling in more long-term support from Intel and hotboxing their codes in early Knights Landing machines to navigate these worries.

Our congrats to Cray and the NNSA – this will be a great story to watch unfold….

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

DoE Awards 24 ASCR Leadership Computing Challenge (ALCC) Projects

June 28, 2017

On Monday, the U.S. Department of Energy’s (DOE’s) ASCR Leadership Computing Challenge (ALCC) program awarded 24 projects a total of 2.1 billion core-hours at the Argonne Leadership Computing Facility (ALCF). The o Read more…

By HPCwire Staff

STEM-Trekker Badisa Mosesane Attends CERN Summer Student Program

June 27, 2017

Badisa Mosesane, an undergraduate scholar who studies computer science at the University of Botswana in Gaborone, recently joined other students from developing nations around the world in Geneva, Switzerland to particip Read more…

By Elizabeth Leake, STEM-Trek

The EU Human Brain Project Reboots but Supercomputing Still Needed

June 26, 2017

The often contentious, EU-funded Human Brain Project whose initial aim was fixed firmly on full-brain simulation is now in the midst of a reboot targeting a more modest goal – development of informatics tools and data/ Read more…

By John Russell

DOE Launches Chicago Quantum Exchange

June 26, 2017

While many of us were preoccupied with ISC 2017 last week, the launch of the Chicago Quantum Exchange went largely unnoticed. So what is such a thing? It is a Department of Energy sponsored collaboration between the Univ Read more…

By John Russell

HPE Extreme Performance Solutions

Creating a Roadmap for HPC Innovation at ISC 2017

In an era where technological advancements are driving innovation to every sector, and powering major economic and scientific breakthroughs, high performance computing (HPC) is crucial to tackle the challenges of today and tomorrow. Read more…

UMass Dartmouth Reports on HPC Day 2017 Activities

June 26, 2017

UMass Dartmouth's Center for Scientific Computing & Visualization Research (CSCVR) organized and hosted the third annual "HPC Day 2017" on May 25th. This annual event showcases on-going scientific research in Massach Read more…

By Gaurav Khanna

How ‘Knights Mill’ Gets Its Deep Learning Flops

June 22, 2017

Intel, the subject of much speculation regarding the delayed, rewritten or potentially canceled “Aurora” contract (the Argonne Lab part of the CORAL “pre-exascale” award), parsed out additional information ab Read more…

By Tiffany Trader

Tsinghua Crowned Eight-Time Student Cluster Champions at ISC

June 22, 2017

Always a hard-fought competition, the Student Cluster Competition awards were announced Wednesday, June 21, at the ISC High Performance Conference 2017. Amid whoops and hollers from the crowd, Thomas Sterling presented t Read more…

By Kim McMahon

GPUs, Power9, Figure Prominently in IBM’s Bet on Weather Forecasting

June 22, 2017

IBM jumped into the weather forecasting business roughly a year and a half ago by purchasing The Weather Company. This week at ISC 2017, Big Blue rolled out plans to push deeper into climate science and develop more gran Read more…

By John Russell

DoE Awards 24 ASCR Leadership Computing Challenge (ALCC) Projects

June 28, 2017

On Monday, the U.S. Department of Energy’s (DOE’s) ASCR Leadership Computing Challenge (ALCC) program awarded 24 projects a total of 2.1 billion core-hour Read more…

By HPCwire Staff

DOE Launches Chicago Quantum Exchange

June 26, 2017

While many of us were preoccupied with ISC 2017 last week, the launch of the Chicago Quantum Exchange went largely unnoticed. So what is such a thing? It is a D Read more…

By John Russell

How ‘Knights Mill’ Gets Its Deep Learning Flops

June 22, 2017

Intel, the subject of much speculation regarding the delayed, rewritten or potentially canceled “Aurora” contract (the Argonne Lab part of the CORAL “ Read more…

By Tiffany Trader

Tsinghua Crowned Eight-Time Student Cluster Champions at ISC

June 22, 2017

Always a hard-fought competition, the Student Cluster Competition awards were announced Wednesday, June 21, at the ISC High Performance Conference 2017. Amid wh Read more…

By Kim McMahon

GPUs, Power9, Figure Prominently in IBM’s Bet on Weather Forecasting

June 22, 2017

IBM jumped into the weather forecasting business roughly a year and a half ago by purchasing The Weather Company. This week at ISC 2017, Big Blue rolled out pla Read more…

By John Russell

Intersect 360 at ISC: HPC Industry at $44B by 2021

June 22, 2017

The care, feeding and sustained growth of the HPC industry increasingly is in the hands of the commercial market sector – in particular, it’s the hyperscale Read more…

By Doug Black

At ISC – Goh on Go: Humans Can’t Scale, the Data-Centric Learning Machine Can

June 22, 2017

I've seen the future this week at ISC, it’s on display in prototype or Powerpoint form, and it’s going to dumbfound you. The future is an AI neural network Read more…

By Doug Black

Cray Brings AI and HPC Together on Flagship Supers

June 20, 2017

Cray took one more step toward the convergence of big data and high performance computing (HPC) today when it announced that it’s adding a full suite of big d Read more…

By Alex Woodie

Quantum Bits: D-Wave and VW; Google Quantum Lab; IBM Expands Access

March 21, 2017

For a technology that’s usually characterized as far off and in a distant galaxy, quantum computing has been steadily picking up steam. Just how close real-wo Read more…

By John Russell

Trump Budget Targets NIH, DOE, and EPA; No Mention of NSF

March 16, 2017

President Trump’s proposed U.S. fiscal 2018 budget issued today sharply cuts science spending while bolstering military spending as he promised during the cam Read more…

By John Russell

HPC Compiler Company PathScale Seeks Life Raft

March 23, 2017

HPCwire has learned that HPC compiler company PathScale has fallen on difficult times and is asking the community for help or actively seeking a buyer for its a Read more…

By Tiffany Trader

Google Pulls Back the Covers on Its First Machine Learning Chip

April 6, 2017

This week Google released a report detailing the design and performance characteristics of the Tensor Processing Unit (TPU), its custom ASIC for the inference Read more…

By Tiffany Trader

CPU-based Visualization Positions for Exascale Supercomputing

March 16, 2017

In this contributed perspective piece, Intel’s Jim Jeffers makes the case that CPU-based visualization is now widely adopted and as such is no longer a contrarian view, but is rather an exascale requirement. Read more…

By Jim Jeffers, Principal Engineer and Engineering Leader, Intel

Nvidia Responds to Google TPU Benchmarking

April 10, 2017

Nvidia highlights strengths of its newest GPU silicon in response to Google's report on the performance and energy advantages of its custom tensor processor. Read more…

By Tiffany Trader

Nvidia’s Mammoth Volta GPU Aims High for AI, HPC

May 10, 2017

At Nvidia's GPU Technology Conference (GTC17) in San Jose, Calif., this morning, CEO Jensen Huang announced the company's much-anticipated Volta architecture a Read more…

By Tiffany Trader

Facebook Open Sources Caffe2; Nvidia, Intel Rush to Optimize

April 18, 2017

From its F8 developer conference in San Jose, Calif., today, Facebook announced Caffe2, a new open-source, cross-platform framework for deep learning. Caffe2 is the successor to Caffe, the deep learning framework developed by Berkeley AI Research and community contributors. Read more…

By Tiffany Trader

Leading Solution Providers

MIT Mathematician Spins Up 220,000-Core Google Compute Cluster

April 21, 2017

On Thursday, Google announced that MIT math professor and computational number theorist Andrew V. Sutherland had set a record for the largest Google Compute Engine (GCE) job. Sutherland ran the massive mathematics workload on 220,000 GCE cores using preemptible virtual machine instances. Read more…

By Tiffany Trader

Google Debuts TPU v2 and will Add to Google Cloud

May 25, 2017

Not long after stirring attention in the deep learning/AI community by revealing the details of its Tensor Processing Unit (TPU), Google last week announced the Read more…

By John Russell

Russian Researchers Claim First Quantum-Safe Blockchain

May 25, 2017

The Russian Quantum Center today announced it has overcome the threat of quantum cryptography by creating the first quantum-safe blockchain, securing cryptocurrencies like Bitcoin, along with classified government communications and other sensitive digital transfers. Read more…

By Doug Black

US Supercomputing Leaders Tackle the China Question

March 15, 2017

Joint DOE-NSA report responds to the increased global pressures impacting the competitiveness of U.S. supercomputing. Read more…

By Tiffany Trader

Groq This: New AI Chips to Give GPUs a Run for Deep Learning Money

April 24, 2017

CPUs and GPUs, move over. Thanks to recent revelations surrounding Google’s new Tensor Processing Unit (TPU), the computing world appears to be on the cusp of Read more…

By Alex Woodie

DOE Supercomputer Achieves Record 45-Qubit Quantum Simulation

April 13, 2017

In order to simulate larger and larger quantum systems and usher in an age of “quantum supremacy,” researchers are stretching the limits of today’s most advanced supercomputers. Read more…

By Tiffany Trader

Messina Update: The US Path to Exascale in 16 Slides

April 26, 2017

Paul Messina, director of the U.S. Exascale Computing Project, provided a wide-ranging review of ECP’s evolving plans last week at the HPC User Forum. Read more…

By John Russell

Six Exascale PathForward Vendors Selected; DoE Providing $258M

June 15, 2017

The much-anticipated PathForward awards for hardware R&D in support of the Exascale Computing Project were announced today with six vendors selected – AMD Read more…

By John Russell

  • arrow
  • Click Here for More Headlines
  • arrow
Share This