Los Alamos Lead Shares ‘Trinity’ Feeds and Speeds

By Nicole Hemsoth

July 10, 2014

We’ve been anticipating news around the Trinity supercomputer for some time now and today were graced with the news that Cray will be supplying the machine in two phases with the final phase being complete in 2016. For the original background, the first run of the story can be found here.

Since that time this morning, we were able to have an in-depth discussion with one of the key thinkers at the heart of the procurement, Los Alamos National Labs’ HPC division leader, Gary Grider. His foundational work on burst buffers (a term he coined) features prominently in the other half of the procurement, the NERSC “Cori” system, but he’s also been instrumental in making system-level choices for the NNSA’s mission-critical Trinity supercomputer, along with a great deal of assistance from project partners at Sandia.

Grider told us the team at Los Alamos is already busy installing the extra power and cooling needed to ready space inside the existing Strategic Computing Complex at the lab with the 45,000 square feet of space for the new system. The approximately 270 next-generation Cray XC racks won’t occupy that entire space, says Grider, but the 10,000 square feet it needs will be prepared with the warm water cooling infrastructure needed to keep the Haswell and Knights Landing-based nodes cool, while feeding recycled water that isn’t in the racks out into protected wetlands—thus offsetting some of the concerns about the 8-10 MW that the new super will likely consume. In the bigger picture, however, Los Alamos is thinking ahead—the facility itself is preparing to handle far more in terms of power and cooling with the capability of 30 MW in sight.

We weren’t able to tell this morning how large the machine might be, but started piecing things together with some information that’s available. We know that the next-generation Haswell core count will fall somewhere in the 14-18 range (perhaps up to 24—we’ll find this out in upcoming Intel announcements, probably this quarter) and with the additional Knights Landing chips, which will sport on-package memory and anywhere between 60-72 cores, according to the data we have available. In the end, Grider confirmed that the system will (like way far) exceed the original performance targets of 30 petaflops, but he’s not sure how far over the mark it will go for the machine. There’s some speculative math coming your way soon on this…but even if half the machine is just the Xeon…whew.

As we noted earlier today, we’ll do the math once the most recent Haswell core counts and expected performance/thermals come out soon—and add it to whatever Intel cares to share later this year about the future performance of its self-hosted Knights Landing part.

For those who keep supercomputing score (and Grider isn’t one of them—he doesn’t care about the FLOPS, he cares about getting 6x-8x the performance of their workhouse “Cielo” machine) recall that this would put the 2015-2016 NNSA supercomputer just around the existing #1 system in the world for 2 years running—China’s Tianhe-2. No small feat, but Grider says that they’re not planning LINPACK unless the vendors ask them to. And if Cray thought that spike in their stock price was attractive today, having twice a year news around another top super couldn’t hurt.

The two phases of the project mean that the first cores that will hit the floor will be the Haswells because the facility cannot wait for the Knights Landing to come into play. He says that for the other side of the procurement at NERSC, they had more flexibility in waiting on the chips because they have enough capacity to keep the Office of Science machines and researchers fed. The problem at the NNSA, however, is that they need more computing power immediately. They’re going to complete an install of the first set of Haswell-based machines in the summer of 2015—but the delay is just facilities-related. They need to get their power and cooling infrastructure secured before these can go in, he said, stressing that there are no delays on Intel’s part expected for the first component.

The precise configuration of the nodes in the Trinity machine have not been divulged, but it looks like there will be compute nodes with multiple Haswell Xeon E5 v3 processors on them as well as compute nodes that have multiple Knights Landing Xeon Phi processors on them. All of these devices will be connected using the Aries XC interconnect in its dragonfly topology.

It is not clear exactly how the processors will link to the Aries interconnect, but the current Aries chip is a 48-port router that has four PCI-Express 3.0 lanes linking to four two-socket Xeon nodes. The Aries chip also has three different ranks of connectivity: Rank 1 goes into the backplane, Rank 2 is a copper network for linking six XC enclosures to each other, and Rank 3 is an optical network that links multiple rack pairs to each other. Each server node has four two-socket servers and Aries interconnect in the current design. Conceptually, you could put Xeon E5s and Xeon Phis on the same server form factor. The important thing is that the Aries interconnect allows all nodes in the system to talk to one another. The system has what Cray calls adaptive routing, making use of multiple routes in the network to get around congestion, and that implies that the system can start out with Xeon processors and have Xeon Phi chips added later with relative ease.

One little note about the architectural choice goes back to an actual lack of choice. Grider says he’s been watching OpenPower efforts carefully, but they’re mission-driven at the NNSA and need the power and bandwidth now. The OpenPower roadmap, while presenting some attractive features, was too long to consider.

Discrete GPUs were not an option for the same reasons, said Grider, noting, “we probably would have considered this as an option if there was a self-hosted GPU of some kind or higher bandwidth than a PCI bus. Again, if you look at the time we were making these decisions and the chips avail in the timeframe, you’ll see that there’s really nothing else out there right now.”

While the architectural choice is already being questioned by some as being more conservative than expected, there are a few things to keep in mind. Unlike open science centers (including NERSC) the application demands are limited in terms of scope. Grider says there are less than a dozen codes set to run on the monster, but these have been refined and blessed over the course of many years. We don’t mess around when it comes to our nuclear facilities. This means retooling codes to fit into architectural boxes is impractical and further, that they have a very defined sense of exactly what they need. The choices for architecture, while very conservative, were the only choices.

But it’s not like there’s nothing interesting happening here. For instance, Grider, the originator of the burst buffer term and early research, said that they’re going to be seeking as much performance out of their flash array as possible—using the burst buffer technology for the first time on a large-scale machine in 2015 to see how it adds to their reliability and 90% utilization goals. And from a memory perspective, it’s nothing to sneeze at either—with 2-3 petabytes of main memory, that 7 petabyte flash gear to support the burst buffer, and 82 petabytes of disk, it’s quite the powerhouse overall—and even conservative for a burst buffer until they see exactly how Cray’s Tiered Storage stuff works in action.

“The burst buffer might be in the 5-7 TB/sec and the disk system is 1-2 TB/sec. The models show that you could sustain the 90% goal with less disk bandwidth, more like 10x less than the burst buffer BW instead of the 4-5x on this machine. This was a deliberate choice because of the immaturity of the burst buffer solution space. This is the first burst buffer solution being deployed and it is a pretty large scale deployment as well, so there is reason to be a little conservative. If we had complete confidence in the burst buffer solutions at this scale, we could have saved money by buying less disk BW. Future machines can be more aggressive in this area,” said Grider.

But there are risks, even with a conservative architecture. When asked what he worries about most in terms of implementation and early use nitty-gritty, Grider said there is concern that the architecture takes a turn from the heterogeneous approach where they had a strong integer machine and a strong processor (as with Roadrunner’s AMDs) where the network was attached.

“Since Knights Landing is such a flat architecture, where it’s just a bunch of equivalent-sized processors that are smaller and weaker whereas for hot processes you want a stronger processor, we’re going to have to do some thinking,” he said. In the next month, Grider added they’ll be pulling in more long-term support from Intel and hotboxing their codes in early Knights Landing machines to navigate these worries.

Our congrats to Cray and the NNSA – this will be a great story to watch unfold….

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

How Formula 1 Used Cloud HPC to Build the Next Generation of Racing

December 12, 2019

Formula 1, Rob Smedley explained, is maybe the biggest racing spectacle in the world, with five hundred million fans tuning in for every race. Smedley, a chief engineer with Formula 1’s performance engineering and anal Read more…

By Oliver Peckham

RPI Powers Up ‘AiMOS’ AI Supercomputer

December 11, 2019

Designed to push the frontiers of computing chip and systems performance optimized for AI workloads, an 8 petaflops (Linpack) IBM Power9-based supercomputer has been unveiled in upstate New York that will be used by IBM Read more…

By Doug Black

At SC19: Developing a Digital Twin

December 11, 2019

In the not too distant future, we can expect to see our skies filled with unmanned aerial vehicles (UAVs) delivering packages, maybe even people, from location to location. In such a world, there will also be a digita Read more…

By Aaron Dubrow

Supercomputers Help Predict Carbon Dioxide Levels

December 10, 2019

The Earth’s terrestrial ecosystems – its lands, forests, jungles and so on – are crucial “sinks” for atmospheric carbon, holding nearly 30 percent of our annual CO2 emissions as they breathe in the carbon-rich Read more…

By Oliver Peckham

Finally! SC19 Competitors Live and in Color!

December 10, 2019

You know the saying “better late than never”? That’s how my cluster competition coverage is faring this year. With SC19 coming late in November, quickly followed by my annual trip to South Africa to cover their clu Read more…

By Dan Olds

AWS Solution Channel

Making High Performance Computing Affordable and Accessible for Small and Medium Businesses with HPC on AWS

High performance computing (HPC) brings a powerful set of tools to a broad range of industries, helping to drive innovation and boost revenue in finance, genomics, oil and gas extraction, and other fields. Read more…

IBM Accelerated Insights

GPU Scheduling and Resource Accounting: The Key to an Efficient AI Data Center

[Connect with LSF users and learn new skills in the IBM Spectrum LSF User Community!]

GPUs are the new CPUs

GPUs have become a staple technology in modern HPC and AI data centers. Read more…

Intel’s Jim Clarke on its New Cryo-controller and why Intel isn’t Late to the Quantum Party

December 9, 2019

Intel today introduced the ‘first-of-its-kind’ cryo-controller chip for quantum computing and previewed a cryo-prober tool for characterizing quantum processor chips. The new controller is a mixed-signal SoC named Ho Read more…

By John Russell

RPI Powers Up ‘AiMOS’ AI Supercomputer

December 11, 2019

Designed to push the frontiers of computing chip and systems performance optimized for AI workloads, an 8 petaflops (Linpack) IBM Power9-based supercomputer has Read more…

By Doug Black

Intel’s Jim Clarke on its New Cryo-controller and why Intel isn’t Late to the Quantum Party

December 9, 2019

Intel today introduced the ‘first-of-its-kind’ cryo-controller chip for quantum computing and previewed a cryo-prober tool for characterizing quantum proces Read more…

By John Russell

On the Spack Track @SC19

December 5, 2019

At the annual supercomputing conference, SC19 in Denver, Colorado, there were Spack events each day of the conference. As a reflection of its grassroots heritage, nine sessions were planned by more than a dozen thought leaders from seven organizations, including three U.S. national Department of Energy (DOE) laboratories and Sylabs... Read more…

By Elizabeth Leake

Intel’s New Hyderabad Design Center Targets Exascale Era Technologies

December 3, 2019

Intel's Raja Koduri was in India this week to help launch a new 300,000 square foot design and engineering center in Hyderabad, which will focus on advanced com Read more…

By Tiffany Trader

AWS Debuts 7nm 2nd-Gen Graviton Arm Processor

December 3, 2019

The “x86 Big Bang,” in which market dominance of the venerable Intel CPU has exploded into fragments of processor options suited to varying workloads, has n Read more…

By Doug Black

Ride on the Wild Side – Squyres SC19 Mars Rovers Keynote

December 2, 2019

Reminding us of the deep and enabling connection between HPC and modern science is an important part of the SC Conference mission. And yes, HPC is a science its Read more…

By John Russell

NSCI Update – Adapting to a Changing Landscape

December 2, 2019

It was November of 2017 when we last visited the topic of the National Strategic Computing Initiative (NSCI). As you will recall, the NSCI was started with an Executive Order (E.O. No. 13702), that was issued by President Obama in July of 2015 and was followed by a Strategic Plan that was released in July of 2016. The question for November of 2017... Read more…

By Alex R. Larzelere

Tsinghua University Racks Up Its Ninth Student Cluster Championship Win at SC19

November 27, 2019

Tsinghua University has done it again. At SC19 last week, the eight-time gold medal-winner team took home the top prize in the 2019 Student Cluster Competition Read more…

By Oliver Peckham

Using AI to Solve One of the Most Prevailing Problems in CFD

October 17, 2019

How can artificial intelligence (AI) and high-performance computing (HPC) solve mesh generation, one of the most commonly referenced problems in computational engineering? A new study has set out to answer this question and create an industry-first AI-mesh application... Read more…

By James Sharpe

D-Wave’s Path to 5000 Qubits; Google’s Quantum Supremacy Claim

September 24, 2019

On the heels of IBM’s quantum news last week come two more quantum items. D-Wave Systems today announced the name of its forthcoming 5000-qubit system, Advantage (yes the name choice isn’t serendipity), at its user conference being held this week in Newport, RI. Read more…

By John Russell

DARPA Looks to Propel Parallelism

September 4, 2019

As Moore’s law runs out of steam, new programming approaches are being pursued with the goal of greater hardware performance with less coding. The Defense Advanced Projects Research Agency is launching a new programming effort aimed at leveraging the benefits of massive distributed parallelism with less sweat. Read more…

By George Leopold

Ayar Labs to Demo Photonics Chiplet in FPGA Package at Hot Chips

August 19, 2019

Silicon startup Ayar Labs continues to gain momentum with its DARPA-backed optical chiplet technology that puts advanced electronics and optics on the same chip Read more…

By Tiffany Trader

SC19: IBM Changes Its HPC-AI Game Plan

November 25, 2019

It’s probably fair to say IBM is known for big bets. Summit supercomputer – a big win. Red Hat acquisition – looking like a big win. OpenPOWER and Power processors – jury’s out? At SC19, long-time IBMer Dave Turek sketched out a different kind of bet for Big Blue – a small ball strategy, if you’ll forgive the baseball analogy... Read more…

By John Russell

Cray, Fujitsu Both Bringing Fujitsu A64FX-based Supercomputers to Market in 2020

November 12, 2019

The number of top-tier HPC systems makers has shrunk due to a steady march of M&A activity, but there is increased diversity and choice of processing compon Read more…

By Tiffany Trader

Crystal Ball Gazing: IBM’s Vision for the Future of Computing

October 14, 2019

Dario Gil, IBM’s relatively new director of research, painted a intriguing portrait of the future of computing along with a rough idea of how IBM thinks we’ Read more…

By John Russell

Intel Debuts New GPU – Ponte Vecchio – and Outlines Aspirations for oneAPI

November 17, 2019

Intel today revealed a few more details about its forthcoming Xe line of GPUs – the top SKU is named Ponte Vecchio and will be used in Aurora, the first plann Read more…

By John Russell

Leading Solution Providers

SC 2019 Virtual Booth Video Tour

AMD
AMD
CEJN
CJEN
ONE STOP SYSTEMS
ONE STOP SYSTEMS
PANASAS
PANASAS
SIX NINES IT
SIX NINES IT
VERNE GLOBAL
VERNE GLOBAL
WEKAIO
WEKAIO

Kubernetes, Containers and HPC

September 19, 2019

Software containers and Kubernetes are important tools for building, deploying, running and managing modern enterprise applications at scale and delivering enterprise software faster and more reliably to the end user — while using resources more efficiently and reducing costs. Read more…

By Daniel Gruber, Burak Yenier and Wolfgang Gentzsch, UberCloud

Dell Ramps Up HPC Testing of AMD Rome Processors

October 21, 2019

Dell Technologies is wading deeper into the AMD-based systems market with a growing evaluation program for the latest Epyc (Rome) microprocessors from AMD. In a Read more…

By John Russell

Cray Wins NNSA-Livermore ‘El Capitan’ Exascale Contract

August 13, 2019

Cray has won the bid to build the first exascale supercomputer for the National Nuclear Security Administration (NNSA) and Lawrence Livermore National Laborator Read more…

By Tiffany Trader

SC19: Welcome to Denver

November 17, 2019

A significant swath of the HPC community has come to Denver for SC19, which began today (Sunday) with a rich technical program. As is customary, the ribbon cutt Read more…

By Tiffany Trader

When Dense Matrix Representations Beat Sparse

September 9, 2019

In our world filled with unintended consequences, it turns out that saving memory space to help deal with GPU limitations, knowing it introduces performance pen Read more…

By James Reinders

With the Help of HPC, Astronomers Prepare to Deflect a Real Asteroid

September 26, 2019

For years, NASA has been running simulations of asteroid impacts to understand the risks (and likelihoods) of asteroids colliding with Earth. Now, NASA and the European Space Agency (ESA) are preparing for the next, crucial step in planetary defense against asteroid impacts: physically deflecting a real asteroid. Read more…

By Oliver Peckham

Cerebras to Supply DOE with Wafer-Scale AI Supercomputing Technology

September 17, 2019

Cerebras Systems, which debuted its wafer-scale AI silicon at Hot Chips last month, has entered into a multi-year partnership with Argonne National Laboratory and Lawrence Livermore National Laboratory as part of a larger collaboration with the U.S. Department of Energy... Read more…

By Tiffany Trader

Jensen Huang’s SC19 – Fast Cars, a Strong Arm, and Aiming for the Cloud(s)

November 20, 2019

We’ve come to expect Nvidia CEO Jensen Huang’s annual SC keynote to contain stunning graphics and lively bravado (with plenty of examples) in support of GPU Read more…

By John Russell

  • arrow
  • Click Here for More Headlines
  • arrow
Do NOT follow this link or you will be banned from the site!
Share This