Exascale Resilience Turns a Corner

By Tiffany Trader

July 21, 2014

While advancing the field of HPC into the exascale era is beset by many obstacles, resiliency might be the most thorny of all. As the number of cores proliferate so too do the number of incorrect behaviors, threatening not just the operation of the machine, but the validity of the results as well. When you consider that exascale machines will employ billion-way parallelism, the necessity to address this problem is clear.

“Over the past few years resilience has became a major issue for HPC systems, in particular in the perspective of large Petascale systems and future Exascale ones.” These words are the opening text of a 2009 technical report by the Illinois-INRIA Joint Laboratory on PetaScale Computing.

The study did a very good job outlining the resilience challenge, which while no means the only problem for exascale computing, is certainly one of the most vexing. To whit, the troubling assertion (written in 2009) that “the time to checkpoint and restart may exceed the mean time to interrupt of top supercomputers before 2015.”

Recently, the authors – HPC’ers Franck Cappello, Al Geist, William Gropp, Sanjay Kale, Bill Kramer, and Marc Snir – revisited that earlier work to elucidate some of the changes that have taken place over the last five years. While there is still a lot of work to be done, the picture that emerges is decidedly more optimistic than it was in 2009.

“The past five years have seen extraordinary technical progress in many domains related to exascale resilience,” the authors report. “Several technical options, initially considered inapplicable or unrealistic in the HPC context, have demonstrated surprising successes. Despite this progress, the exascale resilience problem is not solved, and the community is still facing the difficult challenge of ensuring that exascale applications complete and generate correct results while running on unstable systems.”

The paper defines resilience in the context of computer platforms as “the techniques for keeping applications running to a correct solution in a timely and efficient manner despite underlying system faults.” Faults, which are the result of errors, are dealt with by predicting, preventing, removing or tolerating them. Faults can occur at all levels of the stack, and thus fault tolerance extends to the hardware, system and application software.

The first section of the paper is devoted to describing the exascale resilience problem. In the words of the authors: “Future exascale systems are expected to exhibit much higher fault rates than current systems do, for various reasons relating to both hardware and software.”

All else being equal, a system that was one-thousand times more powerful, would have one-thousand times more failures. While that simple statistic would be distressing enough, the problem is worse than that. Smaller feature sizes make CPUs more error prone, and shrunken transistors and wires age faster causing even more permanent failures down the road. The same techniques that reduce current leakage also contribute to increased faults. There are steps that vendors can take to reduce error frequency, such as adding circuits, but doing so adds material and energy cost.

Hardware is by no means the only challenge. More complex hardware is matched by more complex system software, which is also more error-prone. Application codes are also increasingly sophisticated and again more error-prone. Research suggests that large parallel jobs may fail as often as once every 30 minutes on exascale platforms.

On the positive side, there have been some important lessons learned now that the community has a few years of experience working with petascale machines. Current petascale platforms experience multiple component failures every day, according to the authors. One study on Blue Waters showed an event that required remedial repair action occurred on average every 4.2 hours and that system-wide events occurred approximately every 160 hours.

The authors report that in its first year of full production, Blue Waters failure rates fell by 50 percent. They note that other supercomputing centers have experienced similar improvements.

The bulk of this 28-page paper is dedicated to laying out a survey of what the community has learned since 2009 (section four) and a summary of the research problems still considered critical by the community (section five).

The authors note that a lot of progress has occurred in handling fail-stop errors by checkpointing.

From the paper: “The norm in 2009 was to store the application state on remote storage, generally a parallel file system, through I/O nodes. Checkpoint time was significant (often 15–30 minutes), because of the limited bandwidth of the parallel file system. When checkpoint time is close to the MTBF, the system spends all its time checkpointing and restarting, with little forward progress. Since the MTJI may be an hour or less on exascale platforms, new techniques are needed in order to reduce checkpoint time.”

This can be accomplished by reducing the checkpoint size. For this, programmers are in the best position to know what is the critical data, but this requires a manual approach. “Annotations about ways to protect or check key data, computations, or communications are still a relevant direction,” the authors state.

Another avenue is to reduce the usage of disks for checkpoint storage for example by using in-memory checkpointing or multi-level checkpointing technologies, which involves combining several storage technologies to optimize overhead and reliability. Partial restart techniques also enable accelerated recovery.

Forward recovery is another way to handle errors. In this scenario, “the application needs to be notified of the error and runs forward recovery steps that may involve access to past or remote data to correct (sometimes partially) or compensate the error and its effect, depending on the latency of the error detection.”

The MPI standard does not provide any specification on the behavior of an MPI application after a fault so several resilient MPI designs and implementations have been developed to fill this void. The first effort was the FT-MPI (fault-tolerant MPI) library. Another called ULFM enables the application to be notified of errors and to reorganize the execution for forward recovery. The MPI Forum has not yet reached a consensus on the characteristics of a resilient MPI.

Replication is another approach for resilience in HPC but it is beset by several constraints including high overhead.

An area that has made “exceptional progress” is recent years is failure prediction, specifically an approach that combines data mining with signal analysis and methods to spot outliers. The authors claim results from the Universty of Illinois at Urbana-Champaign and the Illinois Institute of Technology clearly demonstrate the feasibility of error prediction for the Blue Waters Cray system and the IBM Blue Gene. In fact, Blue Waters staff has been able to predict failures with more than 60 percent accuracy, however the authors also say that higher accuracy still is needed to switch from pure reactive fault tolerance to truly proactive fault tolerance.

This leads to the question of how to run a failure predictor on large infrastructures. Local and global methods each have their merits and drawbacks.

There’s also a side effect of all this error and fault handling: it places an additional energy demand on the computing system. The authors refer to another paper that shows that for clusters, there was not much difference in the energy footprint of different checkpointing protocols. The same study suggests that energy demand correlates more with execution time than it does with the power consumption of the operation performed by the various protocols. Models developed to further study the issue point to parallel recovery as being superior to coordinating checkpointing protocols from an energy perspective since parallel recovery takes less time.

Another difficult challenge facing extreme-scale HPC is the rise of silent data corruptions (SDCs). Interestingly, studies show that while SDCs lead to hangs and crashes, only a small fraction of them corrupt results. But getting the wrong result has researchers concerned enough to explore mitigation strategies. The classic solution is to detect at least some of these silent errors, replicate executions and compare results. Here again, there is a high overhead cost.

A second thornier problem is the presupposition that execution generates identical results. The authors write: “the trend toward more asynchrony and more load balancing plays against deterministic executions.” A workaround was developed, called approximate replication, which runs the normal computation along with an approximate computation. The comparison uses upper and lower bounds and only results outside the bounds are suspect.

There has also been a movement towards integrative approaches that take into consideration all the layers from the hardware to the application. Currently there are at least five projects coming at this problem from different ways.

Other areas that have made huge strides since 2009 include algorithmic approaches to detecting and recovering from faults and so-called fault-oblivious iterative methods. One important change has been the separation of faults into two categories. Fail-stop refers to a process that fails and stops, causing a loss of all state in the process, while fail-continue means a process fails but continues, often due to a transient error. It is expected that transient faults (also called soft faults) are likely
to be the most troubling type of faults in exascale systems, thus it is promising that considerable progress has been made in this area.

In the final section of the paper, the authors lay out several research areas that are closely aligned with supporting resiliency at exascale. These are:

– Characterization of hardware faults
– Development of a standardized fault-handling model
– Improved fault prediction, containment, detection, notification, and recovery
– Programming abstractions for resilience
– Standardized evaluation of fault-tolerance approaches

There is a lot of emphasis placed on informing the research process as much as possible to support better choices. The characterization of hardware faults would help researchers know which problems had the highest probability of occurring and which wreaked the most havoc, so they can maximize their efforts. The first step here would be to systematically gather information about current systems.

Regarding the second bullet point, the authors write: “A useful fault model would have a standard set of recovery services that all computer suppliers would provide to the software developers to develop resilient exascale applications.”

Of course error detection is not very useful if faults are not detected. To this point, the authors are emphatic that further research is needed to pinpoint silent errors. Getting to exascale requires better error detection, and there is currently no technology that can handle frequent SDC other than brute force and replication.

Another void exists when it comes to programming abstractions for resilience. Current research shows that several programming applications will need to be developed and supported in order to develop resilient exascale applications.

The final focus area would provide a practical way of testing new approaches against known approaches, and just as importantly it would provide a means of measuring the effectiveness of a given approach on different architectures and at different scales. To achieve the goal of a standardized evaluation system, the authors envision the “the development of a portable, scalable test suite that simulates all the errors from the fault model and measures the recovery time, services required, and the resources used for a given resilient exascale application.”

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

CMU’s Latest “Card Shark” – Libratus – is Beating the Poker Pros (Again)

January 20, 2017

It’s starting to look like Carnegie Mellon University has a gambling problem – can’t stay away from the poker table. Read more…

By John Russell

IDG to Be Bought by Chinese Investors; IDC to Spin Out HPC Group

January 19, 2017

US-based publishing and investment firm International Data Group, Inc. (IDG) will be acquired by a pair of Chinese investors, China Oceanwide Holdings Group Co., Ltd. Read more…

By Tiffany Trader

Weekly Twitter Roundup (Jan. 19, 2017)

January 19, 2017

Here at HPCwire, we aim to keep the HPC community apprised of the most relevant and interesting news items that get tweeted throughout the week. Read more…

By Thomas Ayres

France’s CEA and Japan’s RIKEN to Partner on ARM and Exascale

January 19, 2017

France’s CEA and Japan’s RIKEN institute announced a multi-faceted five-year collaboration to advance HPC generally and prepare for exascale computing. Among the particulars are efforts to: build out the ARM ecosystem; work on code development and code sharing on the existing and future platforms; share expertise in specific application areas (material and seismic sciences for example); improve techniques for using numerical simulation with big data; and expand HPC workforce training. It seems to be a very full agenda. Read more…

By Nishi Katsuya and John Russell

HPE Extreme Performance Solutions

Remote Visualization: An Integral Technology for Upstream Oil & Gas

As the exploration and production (E&P) of natural resources evolves into an even more complex and vital task, visualization technology has become integral for the upstream oil and gas industry. Read more…

ARM Waving: Attention, Deployments, and Development

January 18, 2017

It’s been a heady two weeks for the ARM HPC advocacy camp. At this week’s Mont-Blanc Project meeting held at the Barcelona Supercomputer Center, Cray announced plans to build an ARM-based supercomputer in the U.K. while Mont-Blanc selected Cavium’s ThunderX2 ARM chip for its third phase of development. Last week, France’s CEA and Japan’s Riken announced a deep collaboration aimed largely at fostering the ARM ecosystem. This activity follows a busy 2016 when SoftBank acquired ARM, OpenHPC announced ARM support, ARM released its SVE spec, Fujistu chose ARM for the post K machine, and ARM acquired HPC tool provider Allinea in December. Read more…

By John Russell

Women Coders from Russia, Italy, and Poland Top Study

January 17, 2017

According to a study posted on HackerRank today the best women coders as judged by performance on HackerRank challenges come from Russia, Italy, and Poland. Read more…

By John Russell

Spurred by Global Ambitions, Inspur in Joint HPC Deal with DDN

January 17, 2017

Inspur, the fast-growth cloud computing and server vendor from China that has several systems on the current Top500 list, and DDN, a leader in high-end storage, have announced a joint sales and marketing agreement to produce solutions based on DDN storage platforms integrated with servers, networking, software and services from Inspur. Read more…

By Doug Black

Weekly Twitter Roundup (Jan. 12, 2017)

January 12, 2017

Here at HPCwire, we aim to keep the HPC community apprised of the most relevant and interesting news items that get tweeted throughout the week. Read more…

By Thomas Ayres

IDG to Be Bought by Chinese Investors; IDC to Spin Out HPC Group

January 19, 2017

US-based publishing and investment firm International Data Group, Inc. (IDG) will be acquired by a pair of Chinese investors, China Oceanwide Holdings Group Co., Ltd. Read more…

By Tiffany Trader

France’s CEA and Japan’s RIKEN to Partner on ARM and Exascale

January 19, 2017

France’s CEA and Japan’s RIKEN institute announced a multi-faceted five-year collaboration to advance HPC generally and prepare for exascale computing. Among the particulars are efforts to: build out the ARM ecosystem; work on code development and code sharing on the existing and future platforms; share expertise in specific application areas (material and seismic sciences for example); improve techniques for using numerical simulation with big data; and expand HPC workforce training. It seems to be a very full agenda. Read more…

By Nishi Katsuya and John Russell

ARM Waving: Attention, Deployments, and Development

January 18, 2017

It’s been a heady two weeks for the ARM HPC advocacy camp. At this week’s Mont-Blanc Project meeting held at the Barcelona Supercomputer Center, Cray announced plans to build an ARM-based supercomputer in the U.K. while Mont-Blanc selected Cavium’s ThunderX2 ARM chip for its third phase of development. Last week, France’s CEA and Japan’s Riken announced a deep collaboration aimed largely at fostering the ARM ecosystem. This activity follows a busy 2016 when SoftBank acquired ARM, OpenHPC announced ARM support, ARM released its SVE spec, Fujistu chose ARM for the post K machine, and ARM acquired HPC tool provider Allinea in December. Read more…

By John Russell

Spurred by Global Ambitions, Inspur in Joint HPC Deal with DDN

January 17, 2017

Inspur, the fast-growth cloud computing and server vendor from China that has several systems on the current Top500 list, and DDN, a leader in high-end storage, have announced a joint sales and marketing agreement to produce solutions based on DDN storage platforms integrated with servers, networking, software and services from Inspur. Read more…

By Doug Black

For IBM/OpenPOWER: Success in 2017 = (Volume) Sales

January 11, 2017

To a large degree IBM and the OpenPOWER Foundation have done what they said they would – assembling a substantial and growing ecosystem and bringing Power-based products to market, all in about three years. Read more…

By John Russell

UberCloud Cites Progress in HPC Cloud Computing

January 10, 2017

200 HPC cloud experiments, 80 case studies, and a ton of hands-on experience gained, that’s the harvest of four years of UberCloud HPC Experiments. Read more…

By Wolfgang Gentzsch and Burak Yenier

A Conversation with Women in HPC Director Toni Collis

January 6, 2017

In this SC16 video interview, HPCwire Managing Editor Tiffany Trader sits down with Toni Collis, the director and founder of the Women in HPC (WHPC) network, to discuss the strides made since the organization’s debut in 2014. Read more…

By Tiffany Trader

BioTeam’s Berman Charts 2017 HPC Trends in Life Sciences

January 4, 2017

Twenty years ago high performance computing was nearly absent from life sciences. Today it’s used throughout life sciences and biomedical research. Genomics and the data deluge from modern lab instruments are the main drivers, but so is the longer-term desire to perform predictive simulation in support of Precision Medicine (PM). There’s even a specialized life sciences supercomputer, ‘Anton’ from D.E. Shaw Research, and the Pittsburgh Supercomputing Center is standing up its second Anton 2 and actively soliciting project proposals. There’s a lot going on. Read more…

By John Russell

AWS Beats Azure to K80 General Availability

September 30, 2016

Amazon Web Services has seeded its cloud with Nvidia Tesla K80 GPUs to meet the growing demand for accelerated computing across an increasingly-diverse range of workloads. The P2 instance family is a welcome addition for compute- and data-focused users who were growing frustrated with the performance limitations of Amazon's G2 instances, which are backed by three-year-old Nvidia GRID K520 graphics cards. Read more…

By Tiffany Trader

US, China Vie for Supercomputing Supremacy

November 14, 2016

The 48th edition of the TOP500 list is fresh off the presses and while there is no new number one system, as previously teased by China, there are a number of notable entrants from the US and around the world and significant trends to report on. Read more…

By Tiffany Trader

For IBM/OpenPOWER: Success in 2017 = (Volume) Sales

January 11, 2017

To a large degree IBM and the OpenPOWER Foundation have done what they said they would – assembling a substantial and growing ecosystem and bringing Power-based products to market, all in about three years. Read more…

By John Russell

Vectors: How the Old Became New Again in Supercomputing

September 26, 2016

Vector instructions, once a powerful performance innovation of supercomputing in the 1970s and 1980s became an obsolete technology in the 1990s. But like the mythical phoenix bird, vector instructions have arisen from the ashes. Here is the history of a technology that went from new to old then back to new. Read more…

By Lynd Stringer

Container App ‘Singularity’ Eases Scientific Computing

October 20, 2016

HPC container platform Singularity is just six months out from its 1.0 release but already is making inroads across the HPC research landscape. It's in use at Lawrence Berkeley National Laboratory (LBNL), where Singularity founder Gregory Kurtzer has worked in the High Performance Computing Services (HPCS) group for 16 years. Read more…

By Tiffany Trader

Dell EMC Engineers Strategy to Democratize HPC

September 29, 2016

The freshly minted Dell EMC division of Dell Technologies is on a mission to take HPC mainstream with a strategy that hinges on engineered solutions, beginning with a focus on three industry verticals: manufacturing, research and life sciences. "Unlike traditional HPC where everybody bought parts, assembled parts and ran the workloads and did iterative engineering, we want folks to focus on time to innovation and let us worry about the infrastructure," said Jim Ganthier, senior vice president, validated solutions organization at Dell EMC Converged Platforms Solution Division. Read more…

By Tiffany Trader

Lighting up Aurora: Behind the Scenes at the Creation of the DOE’s Upcoming 200 Petaflops Supercomputer

December 1, 2016

In April 2015, U.S. Department of Energy Undersecretary Franklin Orr announced that Intel would be the prime contractor for Aurora: Read more…

By Jan Rowell

Enlisting Deep Learning in the War on Cancer

December 7, 2016

Sometime in Q2 2017 the first ‘results’ of the Joint Design of Advanced Computing Solutions for Cancer (JDACS4C) will become publicly available according to Rick Stevens. He leads one of three JDACS4C pilot projects pressing deep learning (DL) into service in the War on Cancer. Read more…

By John Russell

Leading Solution Providers

D-Wave SC16 Update: What’s Bo Ewald Saying These Days

November 18, 2016

Tucked in a back section of the SC16 exhibit hall, quantum computing pioneer D-Wave has been talking up its new 2000-qubit processor announced in September. Forget for a moment the criticism sometimes aimed at D-Wave. This small Canadian company has sold several machines including, for example, ones to Lockheed and NASA, and has worked with Google on mapping machine learning problems to quantum computing. In July Los Alamos National Laboratory took possession of a 1000-quibit D-Wave 2X system that LANL ordered a year ago around the time of SC15. Read more…

By John Russell

CPU Benchmarking: Haswell Versus POWER8

June 2, 2015

With OpenPOWER activity ramping up and IBM’s prominent role in the upcoming DOE machines Summit and Sierra, it’s a good time to look at how the IBM POWER CPU stacks up against the x86 Xeon Haswell CPU from Intel. Read more…

By Tiffany Trader

Nvidia Sees Bright Future for AI Supercomputing

November 23, 2016

Graphics chipmaker Nvidia made a strong showing at SC16 in Salt Lake City last week. Read more…

By Tiffany Trader

Beyond von Neumann, Neuromorphic Computing Steadily Advances

March 21, 2016

Neuromorphic computing – brain inspired computing – has long been a tantalizing goal. The human brain does with around 20 watts what supercomputers do with megawatts. And power consumption isn’t the only difference. Fundamentally, brains ‘think differently’ than the von Neumann architecture-based computers. While neuromorphic computing progress has been intriguing, it has still not proven very practical. Read more…

By John Russell

The Exascale Computing Project Awards $39.8M to 22 Projects

September 7, 2016

The Department of Energy’s Exascale Computing Project (ECP) hit an important milestone today with the announcement of its first round of funding, moving the nation closer to its goal of reaching capable exascale computing by 2023. Read more…

By Tiffany Trader

BioTeam’s Berman Charts 2017 HPC Trends in Life Sciences

January 4, 2017

Twenty years ago high performance computing was nearly absent from life sciences. Today it’s used throughout life sciences and biomedical research. Genomics and the data deluge from modern lab instruments are the main drivers, but so is the longer-term desire to perform predictive simulation in support of Precision Medicine (PM). There’s even a specialized life sciences supercomputer, ‘Anton’ from D.E. Shaw Research, and the Pittsburgh Supercomputing Center is standing up its second Anton 2 and actively soliciting project proposals. There’s a lot going on. Read more…

By John Russell

Dell Knights Landing Machine Sets New STAC Records

November 2, 2016

The Securities Technology Analysis Center, commonly known as STAC, has released a new report characterizing the performance of the Knight Landing-based Dell PowerEdge C6320p server on the STAC-A2 benchmarking suite, widely used by the financial services industry to test and evaluate computing platforms. The Dell machine has set new records for both the baseline Greeks benchmark and the large Greeks benchmark. Read more…

By Tiffany Trader

What Knights Landing Is Not

June 18, 2016

As we get ready to launch the newest member of the Intel Xeon Phi family, code named Knights Landing, it is natural that there be some questions and potentially some confusion. Read more…

By James Reinders, Intel

  • arrow
  • Click Here for More Headlines
  • arrow
Share This