Teaching the World About Intel Xeon Phi: An Interview with Rob Farber

October 14, 2014

Rob Farber is the founder and CEO of TechEnablement, a firm that provides education, planning, analysis and code tutorials, with an emphasis on HPC. In this interview, Rob gives his perspective on the direction of HPC technology and the urgent need for code modernization. He also discusses the newest book by James Reinders and Jim Jeffers, High Performance Parallelism Pearls, which distills the experience of sixty-nine HPC experts into twenty-eight chapters designed to teach the world about the performance capabilities of the massively-parallel Intel Xeon Phi family of products.

Here’s what Rob had to say:

Basically, when our firm looks at the world of technology through the lens of tech enablement, what we see is a tremendous demand for HPC everywhere that makes full use of today’s and tomorrow’s massively parallel computers. Technology is the key. For example, today, many HPC organizations are starting massive code optimization or modernization efforts using the Intel Xeon Phi coprocessor in order to prepare for Knights Landing, the next generation of Intel’s powerful Xeon Phi processors that will be available in the near future.

Why is this cool? Why will everyone involved with technology be interested? It’s because we are moving into the world of plug-and-play supercomputing. You buy a box, plug in power, plug into a network and “Voilá!” you have a massively parallel SMP and MPI cluster powered by Knights Landing. Think how plug and play peripherals changed the world and extrapolate its impact on HPC. In other words, “HPC Everywhere”.

We have an undeniable need for code modernization so everyone around the world can use this new technology. It’s really exciting. Reinders and Jeffers saw this market need and created a textbook that includes downloadable working code and figures as teaching aids.

High Performance Parallelism PearlsI see the book, High Performance Parallelism Pearls, as vital to helping code developers understand parallel programming with solid lessons that will result in performance gains today while preparing us for the brave new world of Knights Landing. There is a tremendous potential demand for “HPC Everywhere”, but only if people can modernize their applications to use this new massively parallel hardware. Remember that most applications were developed when four cores was a lot, and running wide vector instructions like the AVX-512 was simply not possible.

For an organization to be competitive, or for research organizations to continue advancing scientific discovery, it has become vitally important for their developers to take advantage of new technology because the demand for HPC everywhere is on the rise. For example, because of the compute power now available, rendering is becoming a cottage industry. Embree, Intel’s ray tracing package that runs well on Xeon and Intel Xeon Phi, is discussed in one of the chapters in High Performance Parallelism Pearls.

Augmented reality, which I refer to as the gold rush of the 20-Teens, needs amazing animations; this creates a huge demand for HPC everywhere by people who wish to create highly detailed, photorealistic animations for really cool augmented reality applications. Think of cottage shops filled with people developing animations and selling them – a great boon to the gaming community. Now extrapolate from rendering of characters and monsters to 3D printing of toys and component assembly to get a sense of the value multiplier.

And look at deep learning, my particular area of expertise. The teaching code in my chapter “Deep-learning and Numerical Optimization” is able to exceed a teraflop per second of sustained performance on a single Intel Xeon Phi. On the TACC Stampede supercomputer, I observed that 3,000 Intel Xeon Phi can deliver over 2.2 petaflop/s of average sustained performance. Deep learning is revamping everything from web search engines – Google, Bing, and all the rest – to autonomous vehicles ranging from people flying drones down wooded paths to self-driving cars moving over the roadways.

So, because HPC is everywhere, what we need to do is modernize these applications to make use of capabilities of Knight’s Landing. And there is no compelling reason to delay. Modernization efforts managed today on the Xeon Phi coprocessor will deliver the improved performance on Xeon-based systems as well. The performance gains will carry forward.

For example, in the new Reinders / Jeffers book, an introductory article by Gilles Civario and Michale Lysaght is a tutorial that walks you through a simple N-body code, taking you basically from “hello world” to running the code efficiently. There is another chapter by Rio Yokota and Mustafa Abdul-Jabbar, which discusses their exascale-capable, production-ready implementation of that same computation. Also in the book, production-ready code is part of the educational process – e.g. NWChem from PNNL (Pacific Northwest National Laboratory).

As I mentioned, High Performance Parallelism Pearls is a teaching book that provides code and figures that instructors can work with. In fact, there is so much information in the book that I was forced to create an overview article, “Teaching The World About Intel Xeon Phi” with links to bite-sized consumables about each chapter to help readers decide if they want the book. Even when you own the book, you can examine links in my article to find what interests you very quickly.

The material in the book is an excellent way to get a picture of how HPC is evolving, especially when it comes to code modernization being driven by new technology. Jason Sewall and Guillaume Colin de Verdière poetically say this as “a rising tide lifts all boats.”

This is part of our mission. At TechEnablement we focus on enabling people with technology, making sure to recognize the people who are doing the work – after all technology is a human endeavor. It’s great for their career, helps them get funding, and inspires students and others to move into technology. We provide detailed tutorials so those who want to become involved with technology can dig in to working code and get their hands dirty.

We also provide high level summaries for senior scientists, technologists and people in procurement – the idea is to enable the entire lifecycle of new technology, including funding. So we provide information about funding opportunities to connect the technology with the people and the people to funding. Everybody wins.

High Performance Parallelism Pearls will quickly become one of the most important teaching documents for parallel programming, and will go a long way toward making HPC everywhere a reality.

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