With transistor scaling slated to come up against some fundamental limits over the next five to seven years, chip designers are hot on the trail of technologies to extend the exponential advances described by Moore’s law. One of the most promising areas of R&D involves stacking layers of logic and memory into 3D chips. The implementation faces many challenges, however, including how to remove heat from the inner layers, yet the energy-efficiency and bandwidth payoffs are compelling. Quite a few research groups and all of the big semiconductor makers are working on the technique, but so far cost and risk are holding up progress.
Stanford University is home to one of the group’s working to usher in a new breed of chips that are smaller, faster, and more energy-efficient than today’s traditional ICs. Stanford engineers recently announced the successful development of a four-layer prototype that employs two logic transistor layers on the outside and the two memory layers on the inside. Thousands of nanoscale electronic “elevators” carry information between logic and memory at a rate that is much faster than traditional IC cards, with less electricity.
Project leaders Subhasish Mitra, a Stanford associate professor of electrical engineering and of computer science, and H.-S. Philip Wong, the Williard R. and Inez Kerr Bell Professor in Stanford’s School of Engineering, discuss the new approach in a paper, which the duo presented at the IEEE International Electron Devices Meeting held in San Francisco this week.
As explained in an article from Stanford, the researchers credit three breakthroughs with enabling the technology: a novel transistor design based on carbon nanotubes; memory fabricated using titanium nitride, hafnium oxide and platinum that is more conducive to stacking; and an innovative high-rise technique that employs a “multiplicity of connections.”
Although other research groups have experimented with carbon nanotubes (CNTs), which are considered less leakage prone than silicon due to their small diameter, the Stanford team did something different. They started out the usual way growing CNTs on round quartz wafers. Then using an adhesive process they developed they transferred the CNTs off the quartz growth medium and onto a silicon wafer. This wafer was used as the foundation of the high-rise chip.
The technique provided a way to get lots of CNT’s into a small area, which the team claim gives them some of the highest-density, highest-performance CNT transistors ever built.
“This research is at an early stage, but our design and fabrication techniques are scalable,” Mitra said. “With further development this architecture could lead to computing performance that is much, much greater than anything available today.”
“Paradigm shift is an overused concept, but here it is appropriate,” Wong added. “With this new architecture, electronics manufacturers could put the power of a supercomputer in your hand.”
More details are available here.