Over the last half a century, computers have transformed nearly every facet of society. The information age and its continuing evolution can be traced to the invention of the integrated circuit and the reliable progression of smaller feature sizes – enabling generation after generation of smaller, faster and cheaper microprocessors.
But now that foundational trend of modern computing, commonly referred to as Moore’s law, is in jeopardy. With the US semiconductor industry valued at more than $65 billion a year, and the full promise of big data and the Internet of Things yet to come, there is great motivation to find a replacement technology that can keep this momentum going for another half-century.
In a recent feature piece, NSF science writer Aaron Dubrow discusses some of the work being done to help mitigate the disruption of a plateauing exponential. The International Technology Roadmap for Semiconductors (ITRS), which directs the course for the semiconductor industry, anticipates another decade of shrinking CMOS geometries yielding transistors that are 5 nanometers long and 1 nanometer wide – that’s 5 silicon atoms across.
At the atomic scale, predictability breaks down and there is a rise in strange behaviors, such as quantum tunneling and atomistic disorder. Understanding these phenomena requires specialized modeling software, like NEMO5 (the fifth edition of the NanoElectronics MOdeling Tools). Developed by a team of researchers at Purdue University, led by Gerhard Klimeck, NEMO5 models multiscale, multiphysics phenomena. This makes it possible to design future nanoelectronic devices, including transistors that are only a few atoms wide.
Klimeck and his colleagues received an NSF Petascale Computing Resource Allocation award that enabled them to use their NEMO5 software in tandem with the powerful Blue Waters supercomputer to assess the limits of current semiconductor technologies and explore alternative materials and approaches.
The team’s findings depict some of the challenges that arise with the continued shrinking of CMOS geometries, and were used to inform the 2014 ITRS roadmap.