On January 30, 2015 at the Colfax International headquarters in Sunnyvale, Calif., Intel’s parallel computing savant James Reinders sat down with Vadim Karpusenko, principal HPC research engineer at Colfax International, for an enlightened discussion on the future of parallel programming and Intel MIC architecture products. As Director and Chief Evangelist at Intel Corporation, Reinders is responsible for communicating Intel’s message of how to get the best performance out of hardware.

“At Intel we build great products with a lot of capabilities, but the challenge is how do you explain how to use it, how do you get standards that support it, tools that support it, and how do you get software developers trained in it,” says Reinders of his ambassador-like role.

The dynamics that led to today’s manycore era can be traced back to 2005. Traditional approaches to boosting CPU performance, like driving up clock speeds, hit a wall, and chipmakers made up for the lost performance gains by moving to hyperthreading and multicore architectures. But the hardware changes wouldn’t be fruitful without software that could leverage the additional cores. This necessitated a rethinking of algorithms and approaches, says Reinders.

In this 50 minute video, Reinders reviews the path of Intel’s MIC (Many Integrated Core) architecture from the first-generation Xeon Phi (Knights Corner) to the imminent launch of Knights Landing (KNL) to the expected third-generation product, codenamed Knights Hill (KNH). It takes quite a few years for design to go from concept to becoming a product, says Reinders, but he confirms that the work on Knights Landing is nearly complete and also that there is a team working on the third generation Xeon Phi, Knights Hill. He also provides some interesting details about the underlying process technology.

“We have a lot of innovations up our sleeve and the one that we’ve definitely confirmed is that [Knights Hill] will be on the next-generation process technology,” Reinders shares. “Knights Landing is exciting in coming to 14 nm for the first time for Xeon Phi. Knights Hill will be on the 10 nm process, which gives us more density, more performance, power, and capabilities. You’ll have to wait to see what we’ve done on the cores. But it’s a collection of x86 devices, Intel architecture, so we’ll carry forward the programming story that it has this high-level compatibility with standards and with Intel architecture.”

The point that Reinders really drives home is that the Phi chips were engineered enable dramatic performance gains for highly parallel codes.

“The MIC architecture…is our approach when we architect the chip assuming you are going to run a parallel program on it,” he states. “That’s what really differentiates it from our other products. We’ve optimized it to run a parallel program as fast as possible and it’s absolutely terrible at running a non-parallel program. Whereas our regular processors – our Xeons, our Core processors and our Atom processors – they are designed to balance with the real world. They are designed to allow you to write parallel programs on them and get benefits but they are also designed to handle things like server workloads and multi-tasking workloads that you might find in a tablet or desktop or so forth.

“For the MIC architecture, we threw that out the window and said, what if we designed knowing that the programmer’s only going to throw a parallel program at us, that they are going to try to take advantage of all 61 cores on the current Xeon Phi, what if we designed for that, and it turns out we can put more cores on a device because we can get rid of some of the functionality that can take care of serial, non-parallel programs. And as an engineer, that excites me because you are designing for a different design point and that’s what MIC architecture is all about.

“At Intel, we took the approach of making it compatible, so it really is an SMP cluster on a chip of x86s, it really is Intel architecture on lots of cores, and the only thing we’ve given up is we didn’t design it to run serial workloads well; we designed it assuming you are going to do parallel workloads, so of course it’s a natural fit into technical computing and HPC, but you’re not going to see it on your cell phone or your tablet anytime soon because there just isn’t that level of parallelism being used there.”

1. James Reinders and his role at Intel. – 00:47
2. Why Parallel Programming and Code Modernization is important? – 01:49
3. Brief introduction to MIC architecture and Xeon Phi coprocessors. – 04:03
4. What type of applications benefit from MIC architecture? – 07:16
5. How to approach porting your code for MIC architecture? – 09:58
6. What is new in Knights Landing. – 15:24
7. Details of chip design of Knights Landing. – 19:54
8. 3rd MIC generation – Knights Hill. – 21:16
9. How to future-proof my code? – 23:15
10. High bandwidth memory on KNL. – 27:35
11. Details on James Reinders’ books. – 29:59
12. Future of Parallel Programming. – 34:37
13. New parallel programming languages? – 38:16
14. Future of the parallel libraries. – 40:01
15. How to learn parallel programming? – 45:22
16. Colfax Developer Training. – 48:20