ISC 2015 Keynoter Thomas Sterling on Memory in HPC

By Nages Sieslack, Public Relations Manager at ISC Events

April 15, 2015

The Wednesday keynote at this year’s ISC High Performance conference by HPC veteran Dr. Thomas Sterling promises to be an enlightening and lively presentation of the HPC year in review. And if previous years are a guide, Dr. Sterling will deliver it with the unique humor and style that has become his trademark.

The late Hans Meuer created this concept of a “continuing series” to complement the other focused talks at this conference, where the international HPC community comes together to contemplate the breadth of progress and the latest trends in this rapidly advancing field. Dr. Sterling has served as medium for this topic for more than a decade now.

Dr. Sterling will be also be chairing a session titled Memory Technologies & Systems for HPC, which will take place the day before his keynote presentation. We got in touch with him recently so he could give us some background on this highly topical subject.

ISC: Could you explain why the memory subsystem has become such a bottleneck in applications performance?

The memory has certainly been a significant bottleneck, which has motivated substantial investment in cache hierarchies and coherency hardware. The separation of processor logic from main memory, in terms of both bandwidth and latency of data access channels, has been a fundamental limitation to program efficiency. In the last decade, this “von Neumann bottleneck” has been aggravated due to multi/many-core processors that have imposed increase demands on the processor/memory interface. These demands have increased exponentially to the present day, with only slow improvements to the socket pins and memory channel bandwidths. Worse has been the inclusion of GPU accelerators that has severely complicated information flow at the memory interface. The use of fast scratch pad memories, NVRAM, and burst buffers, among other innovations, will further impose new architecture and programming advances.

Should codes be written differently to help deal with the memory wall problem or should developers leave such efforts up to the compiler?

The memory wall is a fundamental constraint imposed by the architecture both in terms of latency and bandwidth. To the extent that data reuse can be enhanced through reorganization of data access patterns, the effects of this barrier can be mitigated. Depending on the nesting of loops and the striding of data, the use of compilation techniques, perhaps assisted by auto-tuning, may be able to make better utilization of caches and memory channels. However, the programmer is better informed as to the overall possibilities and should structure the code accordingly.

Performance portability is jeopardized by variations in cache architecture across distinct platforms. Also irregular and time-varying data structures, such as dynamic graphs, make it difficult for either the compiler or the programmer to successfully manage memory traffic due to inadequate foreknowledge of the data access demands. In these cases, advanced runtime systems may deliver new optimization strategies using dynamic adaptive coordination.

The growth of “big data” analytics has greatly expanded the demand for in-memory computing. Is in-memory computing a viable alternative to the distributed memory model HPC has lived with for so long?

Big data analytics emphasizes the importance of support for treating the full system memory as a single resource even though it is physically partitioned and distributed. The notion of in-memory computing is a revival of prior art, although across larger scale problems than ever before. It can greatly improve overall system efficiencies and scalability, especially when supported by advanced hardware mechanisms in the communication network control and the memory system. The HPC vendor community is exploring a number of ideas in this area and we can anticipate significant innovations through the rest of this decade.

3D memory is poised to debut in supercomputers very soon. What do you think are the long-term prospects for this technology in HPC?

Stacking of memory dies is crucial to extending the viability of Moore’s Law by significantly increasing the memory capacity significantly on the motherboard. Of importance is the ability of through silicon vias to deliver substantial bandwidth to drive the combined memory banks while minimizing the latency and latency variability across the memory system.

But 3D packaging will extend beyond the limitations of pure memory chips to include CMOS logic devices, like many-core chips and communication networking dies, possibly with optical interconnects. The challenge of such structures is cooling, with the possibility of micro-channel water-cooling or other fluid through the stack.

Are there other promising memory technologies on the horizon that you think might make a difference for HPC?

There are other emerging memory technologies; perhaps the most significant and immediate are the various forms of NVRAMs which deliver higher density and lower cost than conventional DRAMS. These benefit from economy of scale through mass production for a wide array of mobile computing applications, such as digital cameras and phones. How NVRAMs may be used in the HPC memory hierarchy is still a subject of exploration, with challenges of disparate read and write times combined with capability degradation over time, which will complicate its ultimate manifestation. But the cost benefits it affords will drive this technology to some form of major integration and use.

Scratch pad memories, either SRAM or high speed DRAM, will be employed to augment, if not fully replace, automatic caches. It is ironic that caches, which were first devised to simplify memory hierarchy use, like virtual memory, is sometimes an impediment to both performance and productivity. Scratch pad memories permits explicit control of data allocation where usage models are known and scratch pads can be exploited. Hardly a new idea, early Cray computers employed similar techniques. What is interesting is to what degree compiler advances can facilitate this technology opportunity.

Mass storage may be improved through integration of both processor and memory technologies at the disk sites to process streaming information on the fly, for example, for compression and decompression), and disk drive caching, for example, of meta-data. This is particularly applicable to big data analytics as previously discussed.

I am betting that the biggest advance in future memory systems is going to be the reincarnation of a two-decades-old concept known as PIM or processor in memory. It was first explored around 1992 by Peter Kogge of IBM, Ken Lobst of IDA, Jeff Draper of USC ISI, and Bill Dally, then of MIT, with each working on significantly different forms. PIM integrates logic and primitive controllers onto the same semiconductor dies, with the mainstream memory fabric dramatically increasing bandwidth and reducing effective latencies since all the action can be kept on the chip. While special cases, usually related to the SIMD execution model, have been explored through experimental parts, there has never been a successful generalized component with wide applicability and performance advantage. Since this technology also promises better energy efficiency and given that Moore’s Law is asymptoting – I know: it’s not a word) – this may prove to be the era of opportunity for this innovation. There are many issues to be addressed prior to commercial viability, but exciting work is already being undertaken behind the scenes.

Find out more about Dr. Sterling’s Wednesday keynote here.

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

IBM Quantum Update: Q System One Launch, New Collaborators, and QC Center Plans

January 10, 2019

IBM made three significant quantum computing announcements at CES this week. One was introduction of IBM Q System One; it’s really the integration of IBM’s existing 20-quibit platform into a more robust, self-contain Read more…

By John Russell

Intel at CES: Nervana; 10nm Server CPU; Cascade Lake

January 9, 2019

On the eve of the Consumer Electronics Show in Las Vegas this week, Intel staged a launch event that covered a new version of its Nervana AI processor and a demonstration of the next-generation Xeon 10nm chip. The Read more…

By Staff

IBM’s New Global Weather Forecasting System Runs on GPUs

January 9, 2019

Anyone who has checked a forecast to decide whether or not to pack an umbrella knows that weather prediction can be a mercurial endeavor. It is a Herculean task: the constant modeling of incredibly complex systems to a high degree of accuracy at a local level within very short spans of time. Read more…

By Oliver Peckham

HPE Extreme Performance Solutions

HPE Systems With Intel Omni-Path: Architected for Value and Accessible High-Performance Computing

Today’s high-performance computing (HPC) and artificial intelligence (AI) users value high performing clusters. And the higher the performance that their system can deliver, the better. Read more…

IBM Accelerated Insights

Data: The Key To Unlocking Modern Research

Research tackles the big questions, delving into uncharted territory in pursuit of knowledge that could change the world. Today’s research simulations are generating more data than ever before, a trend that shows no signs of slowing. Read more…

The Case Against ‘The Case Against Quantum Computing’

January 9, 2019

It’s not easy to be a physicist. Richard Feynman (basically the Jimi Hendrix of physicists) once said: “The first principle is that you must not fool yourself – and you are the easiest person to fool.” This maxim Read more…

By Ben Criger

IBM Quantum Update: Q System One Launch, New Collaborators, and QC Center Plans

January 10, 2019

IBM made three significant quantum computing announcements at CES this week. One was introduction of IBM Q System One; it’s really the integration of IBM’s Read more…

By John Russell

IBM’s New Global Weather Forecasting System Runs on GPUs

January 9, 2019

Anyone who has checked a forecast to decide whether or not to pack an umbrella knows that weather prediction can be a mercurial endeavor. It is a Herculean task: the constant modeling of incredibly complex systems to a high degree of accuracy at a local level within very short spans of time. Read more…

By Oliver Peckham

The Case Against ‘The Case Against Quantum Computing’

January 9, 2019

It’s not easy to be a physicist. Richard Feynman (basically the Jimi Hendrix of physicists) once said: “The first principle is that you must not fool yourse Read more…

By Ben Criger

The Deep500 – Researchers Tackle an HPC Benchmark for Deep Learning

January 7, 2019

How do you know if an HPC system, particularly a larger-scale system, is well-suited for deep learning workloads? Today, that’s not an easy question to answer Read more…

By John Russell

HPCwire Awards Highlight Supercomputing Achievements in the Sciences

January 3, 2019

In November at SC18 in Dallas, HPCwire Readers’ and Editors’ Choice awards program commemorated its 15th year of honoring achievement in HPC, with categories ranging from Best Use of AI to the Workforce Diversity Leadership Award and recipients across a wide variety of industrial and research sectors. Read more…

By the Editorial Team

White House Top Science Post Filled After Two-Year Vacancy

January 3, 2019

Half-way into Trump's term, the Senate has confirmed a director for the Office of Science and Technology Policy (OSTP), the agency that coordinates science poli Read more…

By Tiffany Trader

Batswana Gems

December 20, 2018

Most who work in the high-performance computing (HPC) industry agree; people problems are far more complicated than technical challenges. As I wrote in a 2015 HPCwire feature titled, “Women in HPC: Revelations and Reckoning,” diversity, or the lack thereof, is the HPC industry’s current grand challenge. Read more…

By Elizabeth Leake

HPC Reflections and (Mostly Hopeful) Predictions

December 19, 2018

So much ‘spaghetti’ gets tossed on walls by the technology community (vendors and researchers) to see what sticks that it is often difficult to peer through Read more…

By John Russell

Quantum Computing Will Never Work

November 27, 2018

Amid the gush of money and enthusiastic predictions being thrown at quantum computing comes a proposed cold shower in the form of an essay by physicist Mikhail Read more…

By John Russell

Cray Unveils Shasta, Lands NERSC-9 Contract

October 30, 2018

Cray revealed today the details of its next-gen supercomputing architecture, Shasta, selected to be the next flagship system at NERSC. We've known of the code-name "Shasta" since the Argonne slice of the CORAL project was announced in 2015 and although the details of that plan have changed considerably, Cray didn't slow down its timeline for Shasta. Read more…

By Tiffany Trader

Summit Supercomputer is Already Making its Mark on Science

September 20, 2018

Summit, now the fastest supercomputer in the world, is quickly making its mark in science – five of the six finalists just announced for the prestigious 2018 Read more…

By John Russell

AMD Sets Up for Epyc Epoch

November 16, 2018

It’s been a good two weeks, AMD’s Gary Silcott and Andy Parma told me on the last day of SC18 in Dallas at the restaurant where we met to discuss their show news and recent successes. Heck, it’s been a good year. Read more…

By Tiffany Trader

US Leads Supercomputing with #1, #2 Systems & Petascale Arm

November 12, 2018

The 31st Supercomputing Conference (SC) - commemorating 30 years since the first Supercomputing in 1988 - kicked off in Dallas yesterday, taking over the Kay Ba Read more…

By Tiffany Trader

House Passes $1.275B National Quantum Initiative

September 17, 2018

Last Thursday the U.S. House of Representatives passed the National Quantum Initiative Act (NQIA) intended to accelerate quantum computing research and developm Read more…

By John Russell

The Case Against ‘The Case Against Quantum Computing’

January 9, 2019

It’s not easy to be a physicist. Richard Feynman (basically the Jimi Hendrix of physicists) once said: “The first principle is that you must not fool yourse Read more…

By Ben Criger

Contract Signed for New Finnish Supercomputer

December 13, 2018

After the official contract signing yesterday, configuration details were made public for the new BullSequana system that the Finnish IT Center for Science (CSC Read more…

By Tiffany Trader

Leading Solution Providers

SC 18 Virtual Booth Video Tour

Advania @ SC18 AMD @ SC18
ASRock Rack @ SC18
DDN Storage @ SC18
HPE @ SC18
IBM @ SC18
Lenovo @ SC18 Mellanox Technologies @ SC18
NVIDIA @ SC18
One Stop Systems @ SC18
Oracle @ SC18 Panasas @ SC18
Supermicro @ SC18 SUSE @ SC18 TYAN @ SC18
Verne Global @ SC18

Nvidia’s Jensen Huang Delivers Vision for the New HPC

November 14, 2018

For nearly two hours on Monday at SC18, Jensen Huang, CEO of Nvidia, presented his expansive view of the future of HPC (and computing in general) as only he can do. Animated. Backstopped by a stream of data charts, product photos, and even a beautiful image of supernovae... Read more…

By John Russell

HPE No. 1, IBM Surges, in ‘Bucking Bronco’ High Performance Server Market

September 27, 2018

Riding healthy U.S. and global economies, strong demand for AI-capable hardware and other tailwind trends, the high performance computing server market jumped 28 percent in the second quarter 2018 to $3.7 billion, up from $2.9 billion for the same period last year, according to industry analyst firm Hyperion Research. Read more…

By Doug Black

HPC Reflections and (Mostly Hopeful) Predictions

December 19, 2018

So much ‘spaghetti’ gets tossed on walls by the technology community (vendors and researchers) to see what sticks that it is often difficult to peer through Read more…

By John Russell

Intel Confirms 48-Core Cascade Lake-AP for 2019

November 4, 2018

As part of the run-up to SC18, taking place in Dallas next week (Nov. 11-16), Intel is doling out info on its next-gen Cascade Lake family of Xeon processors, specifically the “Advanced Processor” version (Cascade Lake-AP), architected for high-performance computing, artificial intelligence and infrastructure-as-a-service workloads. Read more…

By Tiffany Trader

Germany Celebrates Launch of Two Fastest Supercomputers

September 26, 2018

The new high-performance computer SuperMUC-NG at the Leibniz Supercomputing Center (LRZ) in Garching is the fastest computer in Germany and one of the fastest i Read more…

By Tiffany Trader

Houston to Field Massive, ‘Geophysically Configured’ Cloud Supercomputer

October 11, 2018

Based on some news stories out today, one might get the impression that the next system to crack number one on the Top500 would be an industrial oil and gas mon Read more…

By Tiffany Trader

Microsoft to Buy Mellanox?

December 20, 2018

Networking equipment powerhouse Mellanox could be an acquisition target by Microsoft, according to a published report in an Israeli financial publication. Microsoft has reportedly gone so far as to engage Goldman Sachs to handle negotiations with Mellanox. Read more…

By Doug Black

The Deep500 – Researchers Tackle an HPC Benchmark for Deep Learning

January 7, 2019

How do you know if an HPC system, particularly a larger-scale system, is well-suited for deep learning workloads? Today, that’s not an easy question to answer Read more…

By John Russell

  • arrow
  • Click Here for More Headlines
  • arrow
Do NOT follow this link or you will be banned from the site!
Share This