IBM Research has announced the world’s first 7nm node test chips with functioning transistors, accomplished via a partnership with GLOBALFOUNDRIES and Samsung at SUNY Polytechnic Institute’s Colleges of Nanoscale Science and Engineering (SUNY Poly CNSE). Although production 7nm chips are at least two years away, IBM has delivered on its promise to develop the process nodes and beaten its competitors to the punch.
The accomplishment comes a year after the launch of IBM’s $3 billion, five-year initiative to develop 7nm ‘and beyond’ process nodes, geared toward meeting the needs of IBM’s high performance systems that serve big data and cloud computing requirements, and HPC, natch. “To us this is a grand challenge because scaling node to node is becoming almost impossible,” observes Vice President of Semiconductor Technology at IBM Research Mukesh Khare. “The business as usual manufacturing techniques do not apply here, so we collectively, led by IBM Research, have been working on this technology for several years.”
The 7nm test chips are a major step forward, requiring several first-of-a-kind innovations, most notably the use of silicon germanium (SiGe) as the channel material and commercially viable integrated extreme ultraviolet (EUV) lithography.
The move from silicon to silicon germanium channel transistors provides a significant performance improvement compared to previous technology nodes and is a real breakthrough, says Khare. “In order for us to increase the transistor performance we try to apply strain in the channels. If you strain the channels, it increases the speed at which the carriers travel inside the transistor. And introducing silicon germanium is a major step forward where we worked on a fundamental understanding of the material system, its growth, and how to integrate that into a 7nm route so that all its superior material properties still remain and we can get the performance benefit.”
The test chips also employ extreme ultraviolet (EUV) lithography integration at multiple levels. With a wavelength of 13.5nm, EUV simplifies the processing compared to optical lithography, which has a wavelength of 193nm.
“We work closely with our equipment supplier to make sure we have stable lithography tooling,” says Khare. “We also work on optimizing the resist, the materials below the resist, the hard masks, and the etch techniques so that we can print these structures with the new materials and obtain geometries of fin, which are packed below 30nm pitch.”
That tight stacking is enabling near-ideal scaling improvements. According to the IBM-led alliance, the 7nm test chip delivers “close to 50 percent area scaling improvements” over 10nm process nodes. Further, the combination of “SiGe channel material for transistor performance enhancement at 7nm node geometries, process innovations to stack them below 30nm pitch and full integration of EUV lithography at multiple levels…could result in at least a 50 percent power/performance improvement for next generation mainframe and POWER systems that will power the Big Data, cloud and mobile era,” the firm says.
The advances set the stage for CMOS CPUs with up to 20 billion transistors, nearly a four-fold gain over today’s largest, i.e., Intel’s 18-core Xeon Haswell-EP with more than 5.5 billion transistors and IBM’s neuromorphic TrueNorth chip with about 5.4 billion.
IBM and its partners are betting on these 7nm test chips to keep Moore’s law alive for the foreseeable future, and this means there will be intense focus on getting them to market. To that end, Khare says the next step is “to make the technology more stable and manufacturable, and then our partners will transfer this technology and use it for their fab.”
“The job is not done,” he adds, “but the demonstration of 7nm chips with working transistors is a major proof point. Now we perfect it.”