Moving Down the Path Toward Code Modernization

By James Reinders, Director and Chief Evangelist, Intel

August 19, 2015

“Code modernization” is a hot topic. While it is widely understood that applications need to evolve with hardware, there is lot of attention to evaluating how to do that well. Savvy customers ask about both portability and performance portability. Because the time and expertise to do the work is scarce and the willingness to do the work multiple times is even scarcer, there is a strong desire to invest in changes with enduring value and broad applicability.

I’d like to relate some thoughts on what is needed, and how Intel has been joining in efforts to help tackle these challenges.

The Next-Generation Intel Xeon Phi Processor, code named Knights Landing, and the Intel Omni-Path Architecture, Intel’s next generation fabric, are scheduled to ship by the end of this year. The result will be a major boost in the capabilities of systems both large and small. However, the advent of such capabilities will further expose that software applications are generally not yet well tuned for such highly parallel platforms. The needed “modernization” to be scalable is an on-going process.

Our approach with Intel Xeon Phi products has one big advantage: efforts spent to modernize code, with better parallelization, are clearly an investment in the future. This is because such code modernization work generally improves performance on any processor, and the need for such modernization is not temporary. The question is really one of “do it now” or “do it later.”

I’ve had the good fortune to help edit two volumes of examples proving this benefit: High Performance Parallelism Pearls Volume One and Volume Two. Time and time again, software developers who reported on their code modernization work showed that they can modernize codes to utilize parallelism in a way that is not locked to any particular processor architecture. This is the sort of investment in code modernization that is simply an investment in the future, with no proprietary languages or tools required.

If someone asks if your application is ready for Knights Landing, the answer is really a question about your readiness for parallel computations more generally – scaling (including attention to locality of reference), vectorization, and fabric scaling. In other words, have you done code modernization?

Key sticking points on the path to modernized code include:

  • Thread scaling – the ability to scale as you increase the number of cores
  • Vectorization scaling – ensuring the profitable use of vectorization for data parallelism
  • Fabric scaling – essential for cluster applications

Katie Antypas, Department Head at the National Energy Research Scientific Computing Center (NERSC) points out the introduction of architectures like Knights Landing is fueling the impetus for code modernization: “Our users want to focus on their science research and would certainly prefer not to have to modernize their codes for new architectures. The problem is, processor clock speeds have stalled and the only way to increase application performance, and not break power budgets, is to add parallelism and improve data locality. NERSC and other HPC centers spend millions of dollars to power and cool systems. We won’t be able to afford to run more powerful computers without some change in technology that reduces the power output.

“An architecture like Knights Landing which has 72, relatively slow cores, with 4 hardware threads each and 512 bit vector units – all forms of parallelism, along high-bandwidth on-package memory – is a step towards a more energy-efficient supercomputer. But to take advantage of the parallelism and deeper memory hierarchies that Knights Landing provides, applications must be changed.”

Code that remains scalar will use only a small percentage of the capabilities of modern hardware.

One critical bottleneck is that developers with the knowledge and experience to exploit highly parallel capabilities are scarce. And lack of such skills is not the whole challenge; there are other factors at play. Developers are often not the code owner, and many legacy applications may have been worked on by several generations of programmers. It’s not surprising developers are sometimes reluctant to touch the code in the ways necessary to change algorithms to take advantage of all the parallelism opportunities in today’s hardware.

There are a number of initiatives underway to deal with the problem of reaching for maximum performance on current and future HPC systems. For example, Intel recently formed (7/13/15) the Intel Modern Code Developer Community to help with resources, education and community forming and sharing. The Community reaches out to a large community of HPC-focused developers and partners. It brings tools, training, knowledge and support to developers worldwide and offers access to a network of elite developers experienced in parallelism.

The initiative leverages an online community portal that offers training and technical resources, and remote access to hardware. A network of experts around the world work to help educate developers in code modernization techniques such as vectorization, memory and data layout, multithreading, and multimode programming.

Advancing scientific research in key areas such as cancer research, physics, and climate modeling, demands ever-increasing computing resources. To meet this demand, modern systems will continue to grow in scale, and applications must evolve to fully exploit the performance of these systems. While today’s HPC developers may be aware of code modernization needs, many are not yet taking full advantage of the environment and hardware capabilities available to them. The Intel Modern Code Developer Community initiative is a multi-year effort with training tools and support to help address this need.

An effort closely related to the Modern Code Developer Community effort—and whose success was part of the impetus to launch the Modern Code program—is the Intel Parallel Computing Center (IPCC) program.

To date, nearly fifty IPCCs have been established at universities, institutions and labs around the world. One of the latest members is the COSMOS supercomputer facility at the University of Cambridge where researchers under the leadership of Professor Stephen Hawking are analyzing the cosmic microwave sky and simulating the very early Universe. Great examples of their code modernization work is detailed in Chapter 10 of High Performance Parallelism Pearls Volume Two where they explain code changes in nine small steps to modernize their code with stunning results. This code modernization greatly expanded the science they can do as they analyze data from the Planck satellite. (I recently shared my amazement at how casually they mentioned the proof of Gravitational Lensing – not exactly new news, I know!)

IPCC’s charter is to drive the modernization of technical computing community codes. It collaborates with and funds its members to develop curriculum that trains students, scientists and researchers on parallel programming techniques and how to modernize community codes to run on current industry standard parallel architecture. The Centers are focused on modernizing technical computing code that will accelerate discovery in the fields of energy, finance, manufacturing, life sciences, visualization, and beyond.

One IPCC member is Lawrence Berkeley National Laboratories, home of NERSC, which is becoming the poster child for code modernization at the big government labs.

Explains Antypas, “Training in code modernization is a crucial initiative in our support of the DOE Office of Science High Performance Computing applications. We have an incredibly diverse workload and support users who research areas such as astrophysics, chemistry, genomics, climate, fusion research and more. All told we are supporting about 800 projects and 6000 users.”

Providing one-on-one support for this huge user base is obviously impossible. But all these users have to be prepared to work with NERSC’s new Cori Phase-2 supercomputer, which is scheduled to go online in mid-2016. Cori Phase-2 will be a Cray system based on the second generation of Intel Xeon Phi product family, the Knights Landing Many Integrated Core (MIC) Architecture. The system will have over 9300 Knights Landing compute nodes and a sustained performance at least ten times that of the NERSC-6 “Hopper” system.

The NERSC strategy is to partner with about 20 different application teams who represent up to about two thirds of the workload at NERSC. The Center’s code modernization team will pass on lessons learned from working with the core 20 teams to the rest of the NERSC users who will be running applications on Cori.

“Because the hardware has not yet been released, we are really forging a new path,” Antypas says. “We will be receiving some early white boxes from Intel and will work closely with Intel engineers and architects to find out how to best use the incredible power provided by the Cori system. This includes code modernization.

“All of our code at NERSC is already parallel, but today we are using an Intel Ivy Bridge system with 24 cores per node and one or two hyperthreads,” she continues. “The Knights Landing architecture will have up to 72 cores with four hardware threads each. So even if our users are used to dealing with code that works well on existing x86 architecture, they will need training to take advantage of the massive parallelism and on-package memory provided by Knights Landing.”

In an ideal world, you would find an individual who could not only handle parallel code, but also understand the algorithms under development, the computer architecture, the scientific domain, and the ins and outs of application performance. But it’s not an ideal world – hence the reason for the NERSC team approach, application scientists, working with NERSC staff and augmented by working closely with Intel and Cray experts who understand the Knight Landing microarchitecture and the performance tools very deeply.

As Antypas points out, not only will Cori and the modernization of existing and forthcoming code usher in a new era of technical computing, but existing applications will benefit as well. “What we are finding is that as people begin changing their codes to run well on the new architectures, there is a bonus. When we back port the applications and run them on traditional architecture like Ivy Bridge, we see the codes improve by a factor of about two or so,” She says.

NERSC – and every other laboratory, university, and enterprise that relies on high performance computing – is just beginning to move down the complex path of code modernization. By adopting a collaborative approach, such as that being pioneered by NERSC, the journey should be a lot smoother.

Code Modernization – an investment in the future

We are not talking about proprietary modification of codes; we are talking about refinements to applications, and the algorithms in those applications, for highly scalable computational capabilities. Such investments can apply to a very wide variety of current and future machines, with less dependence on any one vendor. I encourage you to join our community to help discuss the future, engage our community, and learn in the process. Take a look at great examples of code modernization in High Performance Parallelism Pearls Volume One and Volume Two, and come join our “Modern Code” Developer Community online.

Author Bio:

James Reinders, Director, Chief Evangelist, Intel Software, is involved in multiple engineering, research and educational efforts to increase use of parallel programming throughout the industry. He joined Intel Corporation in 1989 and his contributions have included working on the world’s first TeraFLOP/s supercomputer (ASCI Red) and the world’s first TeraFLOP/s microprocessor (Intel Xeon Phi coprocessor). James been an author on numerous technical books, including Intel Threading Building Blocks (O’Reilly Media, 2007), Structured Parallel Programming (Morgan Kaufmann, 2012), Intel Xeon Phi Coprocessor High Performance Programming (Morgan Kaufmann, 2013), Multithreading for Visual Effects (A K Peters/CRC Press, 2014), and High Performance Parallelism Pearls (Morgan Kaufmann, 2015).

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