COSMOS Team Achieves 100x Speedup on Cosmology Code

By Tiffany Trader

August 24, 2015

One of the most popular sessions at the Intel Developer Forum last week in San Francisco, and certainly one of the most exciting from an HPC perspective, brought together two of the world’s foremost experts in parallel programming to discuss current state-of-the-art methods for leveraging parallelism on processors and coprocessors. The speakers, Intel’s Jim Jeffers and James Reinders, are also the co-editors of the just-published “High Performance Parallelism Pearls Volume Two: Multicore and Many-core Programming Approaches.”

You aren’t likely to meet two more engaging and engaged programmers who make learning about this stuff fun, even for this non-coder interloper. In writing the two volumes, the duo saw “example after example get performance and performance portability with ‘just parallel programming.'”

Many of the chapters focus on porting codes to the MIC Phi multicore processor, but in the process, the Xeon processors also accrued significant speedups, often 5x or more. As for why developers did not exploit this parallelism until they had the Phi in hand, Reinders and Jeffers refer to this phenomenon as the “inspiration of 60+ cores.”

High Performance Parallelism Pearls Vol2 coverLike the first volume, High Performance Parallelism Pearls Volume Two (Morgan Kaufmann, 2015) offers a sampling of successful programming efforts, demonstrating how to leverage parallelism from Intel Xeon and Xeon Phi processors across multiple vertical domains in science and industry. The book has been published with the spirit of knowledge sharing and all of the figures and source code are available for download to facilitate further exploration.

The IDF15 session (see slides) was focused on providing the developer audience with useful stories and examples for programming for high performance. While the editors are careful in saying they don’t have favorite chapters, the success story related in chapter 10, titled “Cosmic Microwave Background Analysis: Nested Parallelism in Practice,” stands out for its scientific accomplishment and for its programming prowess.

The chapter, which is featured on the cover of the book, highlights the work of researchers in Stephen Hawking’s group at the University of Cambridge, who achieved over a 100x speedup with optimizations carried out in the process of porting their code to the Intel Xeon Phi coprocessor (Knights Corner). The theoretical physicists at Cambridge use a simulation code called MODAL to probe the Cosmic Background Radiation (CMB), a microwave frequency background radiation left over from the Big Bang. In analyzing this data from the origin of the universe and verifying it against theoretical observations, the team is reconstructing the CMB bispectrum for the first time. What is truly remarkable is that in seeking to understand how the universe emerged out of an intense period of expansion, called inflation, the research team has found evidence of extra dimensions.

A production run using the original Modal code (unoptimized, pure MPI) takes about six hours on 512 Intel Xeon E5-4650L cores of the COSMOS SGI supercomputer. If it can be sped-up then it will greatly enhance the cross-validation process, which requires the code be run many times.

Write the authors:

“The calculation performed by Modal is a prime candidate for Intel Xeon Phi coprocessors — the inner product calculations are computationally very expensive, independent of one another, and require very little memory (with production runs using only O(100) MB of RAM and writing only O(1) MB to disk). However, the code as written does not express this calculation in a way that is conducive to the utilization of modern hardware. Our acceleration of Modal therefore has two components: tuning the code to ensure that it runs efficiently (i.e., optimization); and enabling the code to scale across vectors and many cores (i.e., modernization). Extracting performance from current and future generations of Intel Xeon processors and Intel Xeon Phi coprocessors is impossible without parallelism, and the process of optimization and modernization presented here is imperative for ensuring that COSMOS stay at the forefront of cosmological research.”

The chapter — written by James P. Briggs, James R. Fergusson, Juha Jäykkä, Simon J. Pennycook and Edward P. Shellard — details the 10-step process of optimizations, illustrated below:

Accelerating Cosmic Microwave Background Briggs speedup

Accelerating Cosmic Microwave Background Briggs code versions 1-10

The experiment was carried out using a dual socket Intel Xeon processor E5-4650L and an Intel Xeon Phi coprocessor 5110P with the Intel Composer XE 2015 (v15.0.0.090) compiler.

In addition to showcasing the potentially paradigm-changing science that is being enabled, the chapter, and a related paper from the authors, are salient teaching tools, reflecting the hallmarks of effective parallelism, including one that is sometimes omitted from discussion.

Here Jeffers begins reviewing what he and Reinders have long identified as the three most important vectors of parallelism: “data locality, that is making sure your data is structured properly for the parallelism pipeline; threading or scalability; and then vectorization, taking advantage of the syncing capability.”

“But what did we forget?” Reinders calls out.

“What we forgot,” said Jeffers, “is that you should actually analyze your code and see from an algorithm standpoint what you might be able to do to improve your code.”

“So the biggest leap here was this,” Jeffers continues. “[The developers] were moving forward with parallelism, you see they are getting pretty good gains up through [code version] six. They are moving forward. They have the original code. They did some loop modifications and then at number three, Intel MKL integration routines come in. When they hit step seven, they have been v-tuning their code, looking at the hotspots, and then boom, the MKL integration routine is the hotspot. So they picked the one that best met the inputs and outputs they wanted. It turns out they didn’t need all the power of that, the precision, etc. So they wrote their own. They used the new trapezium rule integrator and bang [performance shoots up] — so, it’s not all about the three vectors.”

“So don’t forget your algorithms,” adds Reinders, emphatically. “Do you really need the algorithm you are using? They went from a 10x to a 60x speedup in that one step, and it was an algorithm change and it affected Xeon and Xeon Phi almost equally.”

“And this is a production code,” Jeffers emphasizes, “extremely important to them, to their analysis, and really to the world in understanding the universe.”

From the COSMOS team: “We find that using a simple trapezium rule integrator combined with hand-selected sampling points (to improve accuracy in areas of interest) provides sufficient numerical accuracy to obtain a physically meaningful result, and the reduced space and time requirements of this simplified method give a speed-up of O(10x).”

A summary of the team’s conclusions appears in a presentation posted to manycore.com:

CMD Intel Cambridge Briggs Conclusions
“The total speed-up relative to the original baseline code is close to 100x on both platforms,” the authors write in chapter 10 of the new Pearls volume. “Further the results shown here use only two processor sockets or one coprocessor–by dividing the complete problem space across nodes using MPI, and then subdividing across the processor and coprocessor present in each node, the calculation can be accelerated even further. These optimizations have thus enabled COSMOS to completely change the way in which the code is used; rather than running on the entire system for hours, after careful selection of cosmological parameters, Modal can now be incorporated as part of a larger Monte Carlo pipeline to quickly evaluate the likelihood of alternative parameters.”

On the IDF15 showroom floor, Intel demonstrated a visualization of the cosmic background radiation rendered with the open-source OSPRay Ray Tracing engine running live on two pre-production Intel Knights Landing cards connected by the Omni-Path pre-production fabric. Being able to observe the Planck data with this tool allows scientists to see correlations predicted by Einstein’s theory of general relativity.

Intel COSMOS CBR visualization IDF15 1200x

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

Data Vortex Users Contemplate the Future of Supercomputing

October 19, 2017

Last month (Sept. 11-12), HPC networking company Data Vortex held its inaugural users group at Pacific Northwest National Laboratory (PNNL) bringing together about 30 participants from industry, government and academia t Read more…

By Tiffany Trader

AI Self-Training Goes Forward at Google DeepMind

October 19, 2017

DeepMind, Google’s AI research organization, announced today in a blog that AlphaGo Zero, the latest evolution of AlphaGo (the first computer program to defeat a Go world champion) trained itself within three days to play Go at a superhuman level (i.e., better than any human) – and to beat the old version of AlphaGo – without leveraging human expertise, data or training. Read more…

By Doug Black

Researchers Scale COSMO Climate Code to 4888 GPUs on Piz Daint

October 17, 2017

Effective global climate simulation, sorely needed to anticipate and cope with global warming, has long been computationally challenging. Two of the major obstacles are the needed resolution and prolonged time to compute Read more…

By John Russell

HPE Extreme Performance Solutions

Transforming Genomic Analytics with HPC-Accelerated Insights

Advancements in the field of genomics are revolutionizing our understanding of human biology, rapidly accelerating the discovery and treatment of genetic diseases, and dramatically improving human health. Read more…

Student Cluster Competition Coverage New Home

October 16, 2017

Hello computer sports fans! This is the first of many (many!) articles covering the world-wide phenomenon of Student Cluster Competitions. Finally, the Student Cluster Competition coverage has come to its natural home: H Read more…

By Dan Olds

Data Vortex Users Contemplate the Future of Supercomputing

October 19, 2017

Last month (Sept. 11-12), HPC networking company Data Vortex held its inaugural users group at Pacific Northwest National Laboratory (PNNL) bringing together ab Read more…

By Tiffany Trader

AI Self-Training Goes Forward at Google DeepMind

October 19, 2017

DeepMind, Google’s AI research organization, announced today in a blog that AlphaGo Zero, the latest evolution of AlphaGo (the first computer program to defeat a Go world champion) trained itself within three days to play Go at a superhuman level (i.e., better than any human) – and to beat the old version of AlphaGo – without leveraging human expertise, data or training. Read more…

By Doug Black

Student Cluster Competition Coverage New Home

October 16, 2017

Hello computer sports fans! This is the first of many (many!) articles covering the world-wide phenomenon of Student Cluster Competitions. Finally, the Student Read more…

By Dan Olds

Intel Delivers 17-Qubit Quantum Chip to European Research Partner

October 10, 2017

On Tuesday, Intel delivered a 17-qubit superconducting test chip to research partner QuTech, the quantum research institute of Delft University of Technology (TU Delft) in the Netherlands. The announcement marks a major milestone in the 10-year, $50-million collaborative relationship with TU Delft and TNO, the Dutch Organization for Applied Research, to accelerate advancements in quantum computing. Read more…

By Tiffany Trader

Fujitsu Tapped to Build 37-Petaflops ABCI System for AIST

October 10, 2017

Fujitsu announced today it will build the long-planned AI Bridging Cloud Infrastructure (ABCI) which is set to become the fastest supercomputer system in Japan Read more…

By John Russell

HPC Chips – A Veritable Smorgasbord?

October 10, 2017

For the first time since AMD's ill-fated launch of Bulldozer the answer to the question, 'Which CPU will be in my next HPC system?' doesn't have to be 'Whichever variety of Intel Xeon E5 they are selling when we procure'. Read more…

By Dairsie Latimer

Delays, Smoke, Records & Markets – A Candid Conversation with Cray CEO Peter Ungaro

October 5, 2017

Earlier this month, Tom Tabor, publisher of HPCwire and I had a very personal conversation with Cray CEO Peter Ungaro. Cray has been on something of a Cinderell Read more…

By Tiffany Trader & Tom Tabor

Intel Debuts Programmable Acceleration Card

October 5, 2017

With a view toward supporting complex, data-intensive applications, such as AI inference, video streaming analytics, database acceleration and genomics, Intel i Read more…

By Doug Black

Reinders: “AVX-512 May Be a Hidden Gem” in Intel Xeon Scalable Processors

June 29, 2017

Imagine if we could use vector processing on something other than just floating point problems.  Today, GPUs and CPUs work tirelessly to accelerate algorithms Read more…

By James Reinders

NERSC Scales Scientific Deep Learning to 15 Petaflops

August 28, 2017

A collaborative effort between Intel, NERSC and Stanford has delivered the first 15-petaflops deep learning software running on HPC platforms and is, according Read more…

By Rob Farber

Oracle Layoffs Reportedly Hit SPARC and Solaris Hard

September 7, 2017

Oracle’s latest layoffs have many wondering if this is the end of the line for the SPARC processor and Solaris OS development. As reported by multiple sources Read more…

By John Russell

US Coalesces Plans for First Exascale Supercomputer: Aurora in 2021

September 27, 2017

At the Advanced Scientific Computing Advisory Committee (ASCAC) meeting, in Arlington, Va., yesterday (Sept. 26), it was revealed that the "Aurora" supercompute Read more…

By Tiffany Trader

How ‘Knights Mill’ Gets Its Deep Learning Flops

June 22, 2017

Intel, the subject of much speculation regarding the delayed, rewritten or potentially canceled “Aurora” contract (the Argonne Lab part of the CORAL “ Read more…

By Tiffany Trader

Google Releases Deeplearn.js to Further Democratize Machine Learning

August 17, 2017

Spreading the use of machine learning tools is one of the goals of Google’s PAIR (People + AI Research) initiative, which was introduced in early July. Last w Read more…

By John Russell

Nvidia Responds to Google TPU Benchmarking

April 10, 2017

Nvidia highlights strengths of its newest GPU silicon in response to Google's report on the performance and energy advantages of its custom tensor processor. Read more…

By Tiffany Trader

GlobalFoundries Puts Wind in AMD’s Sails with 12nm FinFET

September 24, 2017

From its annual tech conference last week (Sept. 20), where GlobalFoundries welcomed more than 600 semiconductor professionals (reaching the Santa Clara venue Read more…

By Tiffany Trader

Leading Solution Providers

Graphcore Readies Launch of 16nm Colossus-IPU Chip

July 20, 2017

A second $30 million funding round for U.K. AI chip developer Graphcore sets up the company to go to market with its “intelligent processing unit” (IPU) in Read more…

By Tiffany Trader

Amazon Debuts New AMD-based GPU Instances for Graphics Acceleration

September 12, 2017

Last week Amazon Web Services (AWS) streaming service, AppStream 2.0, introduced a new GPU instance called Graphics Design intended to accelerate graphics. The Read more…

By John Russell

EU Funds 20 Million Euro ARM+FPGA Exascale Project

September 7, 2017

At the Barcelona Supercomputer Centre on Wednesday (Sept. 6), 16 partners gathered to launch the EuroEXA project, which invests €20 million over three-and-a-half years into exascale-focused research and development. Led by the Horizon 2020 program, EuroEXA picks up the banner of a triad of partner projects — ExaNeSt, EcoScale and ExaNoDe — building on their work... Read more…

By Tiffany Trader

Delays, Smoke, Records & Markets – A Candid Conversation with Cray CEO Peter Ungaro

October 5, 2017

Earlier this month, Tom Tabor, publisher of HPCwire and I had a very personal conversation with Cray CEO Peter Ungaro. Cray has been on something of a Cinderell Read more…

By Tiffany Trader & Tom Tabor

Cray Moves to Acquire the Seagate ClusterStor Line

July 28, 2017

This week Cray announced that it is picking up Seagate's ClusterStor HPC storage array business for an undisclosed sum. "In short we're effectively transitioning the bulk of the ClusterStor product line to Cray," said CEO Peter Ungaro. Read more…

By Tiffany Trader

Intel Launches Software Tools to Ease FPGA Programming

September 5, 2017

Field Programmable Gate Arrays (FPGAs) have a reputation for being difficult to program, requiring expertise in specialty languages, like Verilog or VHDL. Easin Read more…

By Tiffany Trader

IBM Advances Web-based Quantum Programming

September 5, 2017

IBM Research is pairing its Jupyter-based Data Science Experience notebook environment with its cloud-based quantum computer, IBM Q, in hopes of encouraging a new class of entrepreneurial user to solve intractable problems that even exceed the capabilities of the best AI systems. Read more…

By Alex Woodie

HPC Chips – A Veritable Smorgasbord?

October 10, 2017

For the first time since AMD's ill-fated launch of Bulldozer the answer to the question, 'Which CPU will be in my next HPC system?' doesn't have to be 'Whichever variety of Intel Xeon E5 they are selling when we procure'. Read more…

By Dairsie Latimer

  • arrow
  • Click Here for More Headlines
  • arrow
Share This