COSMOS Team Achieves 100x Speedup on Cosmology Code

By Tiffany Trader

August 24, 2015

One of the most popular sessions at the Intel Developer Forum last week in San Francisco, and certainly one of the most exciting from an HPC perspective, brought together two of the world’s foremost experts in parallel programming to discuss current state-of-the-art methods for leveraging parallelism on processors and coprocessors. The speakers, Intel’s Jim Jeffers and James Reinders, are also the co-editors of the just-published “High Performance Parallelism Pearls Volume Two: Multicore and Many-core Programming Approaches.”

You aren’t likely to meet two more engaging and engaged programmers who make learning about this stuff fun, even for this non-coder interloper. In writing the two volumes, the duo saw “example after example get performance and performance portability with ‘just parallel programming.'”

Many of the chapters focus on porting codes to the MIC Phi multicore processor, but in the process, the Xeon processors also accrued significant speedups, often 5x or more. As for why developers did not exploit this parallelism until they had the Phi in hand, Reinders and Jeffers refer to this phenomenon as the “inspiration of 60+ cores.”

High Performance Parallelism Pearls Vol2 coverLike the first volume, High Performance Parallelism Pearls Volume Two (Morgan Kaufmann, 2015) offers a sampling of successful programming efforts, demonstrating how to leverage parallelism from Intel Xeon and Xeon Phi processors across multiple vertical domains in science and industry. The book has been published with the spirit of knowledge sharing and all of the figures and source code are available for download to facilitate further exploration.

The IDF15 session (see slides) was focused on providing the developer audience with useful stories and examples for programming for high performance. While the editors are careful in saying they don’t have favorite chapters, the success story related in chapter 10, titled “Cosmic Microwave Background Analysis: Nested Parallelism in Practice,” stands out for its scientific accomplishment and for its programming prowess.

The chapter, which is featured on the cover of the book, highlights the work of researchers in Stephen Hawking’s group at the University of Cambridge, who achieved over a 100x speedup with optimizations carried out in the process of porting their code to the Intel Xeon Phi coprocessor (Knights Corner). The theoretical physicists at Cambridge use a simulation code called MODAL to probe the Cosmic Background Radiation (CMB), a microwave frequency background radiation left over from the Big Bang. In analyzing this data from the origin of the universe and verifying it against theoretical observations, the team is reconstructing the CMB bispectrum for the first time. What is truly remarkable is that in seeking to understand how the universe emerged out of an intense period of expansion, called inflation, the research team has found evidence of extra dimensions.

A production run using the original Modal code (unoptimized, pure MPI) takes about six hours on 512 Intel Xeon E5-4650L cores of the COSMOS SGI supercomputer. If it can be sped-up then it will greatly enhance the cross-validation process, which requires the code be run many times.

Write the authors:

“The calculation performed by Modal is a prime candidate for Intel Xeon Phi coprocessors — the inner product calculations are computationally very expensive, independent of one another, and require very little memory (with production runs using only O(100) MB of RAM and writing only O(1) MB to disk). However, the code as written does not express this calculation in a way that is conducive to the utilization of modern hardware. Our acceleration of Modal therefore has two components: tuning the code to ensure that it runs efficiently (i.e., optimization); and enabling the code to scale across vectors and many cores (i.e., modernization). Extracting performance from current and future generations of Intel Xeon processors and Intel Xeon Phi coprocessors is impossible without parallelism, and the process of optimization and modernization presented here is imperative for ensuring that COSMOS stay at the forefront of cosmological research.”

The chapter — written by James P. Briggs, James R. Fergusson, Juha Jäykkä, Simon J. Pennycook and Edward P. Shellard — details the 10-step process of optimizations, illustrated below:

Accelerating Cosmic Microwave Background Briggs speedup

Accelerating Cosmic Microwave Background Briggs code versions 1-10

The experiment was carried out using a dual socket Intel Xeon processor E5-4650L and an Intel Xeon Phi coprocessor 5110P with the Intel Composer XE 2015 (v15.0.0.090) compiler.

In addition to showcasing the potentially paradigm-changing science that is being enabled, the chapter, and a related paper from the authors, are salient teaching tools, reflecting the hallmarks of effective parallelism, including one that is sometimes omitted from discussion.

Here Jeffers begins reviewing what he and Reinders have long identified as the three most important vectors of parallelism: “data locality, that is making sure your data is structured properly for the parallelism pipeline; threading or scalability; and then vectorization, taking advantage of the syncing capability.”

“But what did we forget?” Reinders calls out.

“What we forgot,” said Jeffers, “is that you should actually analyze your code and see from an algorithm standpoint what you might be able to do to improve your code.”

“So the biggest leap here was this,” Jeffers continues. “[The developers] were moving forward with parallelism, you see they are getting pretty good gains up through [code version] six. They are moving forward. They have the original code. They did some loop modifications and then at number three, Intel MKL integration routines come in. When they hit step seven, they have been v-tuning their code, looking at the hotspots, and then boom, the MKL integration routine is the hotspot. So they picked the one that best met the inputs and outputs they wanted. It turns out they didn’t need all the power of that, the precision, etc. So they wrote their own. They used the new trapezium rule integrator and bang [performance shoots up] — so, it’s not all about the three vectors.”

“So don’t forget your algorithms,” adds Reinders, emphatically. “Do you really need the algorithm you are using? They went from a 10x to a 60x speedup in that one step, and it was an algorithm change and it affected Xeon and Xeon Phi almost equally.”

“And this is a production code,” Jeffers emphasizes, “extremely important to them, to their analysis, and really to the world in understanding the universe.”

From the COSMOS team: “We find that using a simple trapezium rule integrator combined with hand-selected sampling points (to improve accuracy in areas of interest) provides sufficient numerical accuracy to obtain a physically meaningful result, and the reduced space and time requirements of this simplified method give a speed-up of O(10x).”

A summary of the team’s conclusions appears in a presentation posted to manycore.com:

CMD Intel Cambridge Briggs Conclusions
“The total speed-up relative to the original baseline code is close to 100x on both platforms,” the authors write in chapter 10 of the new Pearls volume. “Further the results shown here use only two processor sockets or one coprocessor–by dividing the complete problem space across nodes using MPI, and then subdividing across the processor and coprocessor present in each node, the calculation can be accelerated even further. These optimizations have thus enabled COSMOS to completely change the way in which the code is used; rather than running on the entire system for hours, after careful selection of cosmological parameters, Modal can now be incorporated as part of a larger Monte Carlo pipeline to quickly evaluate the likelihood of alternative parameters.”

On the IDF15 showroom floor, Intel demonstrated a visualization of the cosmic background radiation rendered with the open-source OSPRay Ray Tracing engine running live on two pre-production Intel Knights Landing cards connected by the Omni-Path pre-production fabric. Being able to observe the Planck data with this tool allows scientists to see correlations predicted by Einstein’s theory of general relativity.

Intel COSMOS CBR visualization IDF15 1200x

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

University of Chicago Researchers Generate First Computational Model of Entire SARS-CoV-2 Virus

January 15, 2021

Over the course of the last year, many detailed computational models of SARS-CoV-2 have been produced with the help of supercomputers, but those models have largely focused on critical elements of the virus, such as its Read more…

By Oliver Peckham

Pat Gelsinger Returns to Intel as CEO

January 14, 2021

The Intel board of directors has appointed a new CEO. Intel alum Pat Gelsinger is leaving his post as CEO of VMware to rejoin the company that he parted ways with 11 years ago. Gelsinger will succeed Bob Swan, who will remain CEO until Feb. 15. Gelsinger previously spent 30 years... Read more…

By Tiffany Trader

Roar Supercomputer to Support Naval Aircraft Research

January 14, 2021

One might not think “aircraft” when picturing the U.S. Navy, but the military branch actually has thousands of aircraft currently in service – and now, supercomputing will help future naval aircraft operate faster, Read more…

By Staff report

DOE and NOAA Extend Computing Partnership, Plan for New Supercomputer

January 14, 2021

The National Climate-Computing Research Center (NCRC), hosted by Oak Ridge National Laboratory (ORNL), has been supporting the climate research of the National Oceanic and Atmospheric Administration (NOAA) for the last 1 Read more…

By Oliver Peckham

Using Micro-Combs, Researchers Demonstrate World’s Fastest Optical Neuromorphic Processor for AI

January 13, 2021

Neuromorphic computing, which uses chips that mimic the behavior of the human brain using virtual “neurons,” is growing in popularity thanks to high-profile efforts from Intel and others. Now, a team of researchers l Read more…

By Oliver Peckham

AWS Solution Channel

Now Available – Amazon EC2 C6gn Instances with 100 Gbps Networking

Amazon EC2 C6gn instances powered by AWS Graviton2 processors are now available!

Compared to C6g instances, this new instance type provides 4x higher network bandwidth, 4x higher packet processing performance, and 2x higher EBS bandwidth. Read more…

Intel® HPC + AI Pavilion

Intel Keynote Address

Intel is the foundation of HPC – from the workstation to the cloud to the backbone of the Top500. At SC20, Intel’s Trish Damkroger, VP and GM of high performance computing, addresses the audience to show how Intel and its partners are building the future of HPC today, through hardware and software technologies that accelerate the broad deployment of advanced HPC systems. Read more…

Honing In on AI, US Launches National Artificial Intelligence Initiative Office

January 13, 2021

To drive American leadership in the field of AI into the future, the National Artificial Intelligence Initiative Office has been launched by the White House Office of Science and Technology Policy (OSTP). The new agen Read more…

By Todd R. Weiss

Pat Gelsinger Returns to Intel as CEO

January 14, 2021

The Intel board of directors has appointed a new CEO. Intel alum Pat Gelsinger is leaving his post as CEO of VMware to rejoin the company that he parted ways with 11 years ago. Gelsinger will succeed Bob Swan, who will remain CEO until Feb. 15. Gelsinger previously spent 30 years... Read more…

By Tiffany Trader

Julia Update: Adoption Keeps Climbing; Is It a Python Challenger?

January 13, 2021

The rapid adoption of Julia, the open source, high level programing language with roots at MIT, shows no sign of slowing according to data from Julialang.org. I Read more…

By John Russell

Intel ‘Ice Lake’ Server Chips in Production, Set for Volume Ramp This Quarter

January 12, 2021

Intel Corp. used this week’s virtual CES 2021 event to reassert its dominance of the datacenter with the formal roll out of its next-generation server chip, the 10nm Xeon Scalable processor that targets AI and HPC workloads. The third-generation “Ice Lake” family... Read more…

By George Leopold

Researchers Say It Won’t Be Possible to Control Superintelligent AI

January 11, 2021

Worries about out-of-control AI aren’t new. Many prominent figures have suggested caution when unleashing AI. One quote that keeps cropping up is (roughly) th Read more…

By John Russell

AMD Files Patent on New GPU Chiplet Approach

January 5, 2021

Advanced Micro Devices is accelerating the GPU chiplet race with the release of a U.S. patent application for a device that incorporates high-bandwidth intercon Read more…

By George Leopold

Programming the Soon-to-Be World’s Fastest Supercomputer, Frontier

January 5, 2021

What’s it like designing an app for the world’s fastest supercomputer, set to come online in the United States in 2021? The University of Delaware’s Sunita Chandrasekaran is leading an elite international team in just that task. Chandrasekaran, assistant professor of computer and information sciences, recently was named... Read more…

By Tracey Bryant

Intel Touts Optane Performance, Teases Next-gen “Crow Pass”

January 5, 2021

Competition to leverage new memory and storage hardware with new or improved software to create better storage/memory schemes has steadily gathered steam during Read more…

By John Russell

Farewell 2020: Bleak, Yes. But a Lot of Good Happened Too

December 30, 2020

Here on the cusp of the new year, the catchphrase ‘2020 hindsight’ has a distinctly different feel. Good riddance, yes. But also proof of science’s power Read more…

By John Russell

Esperanto Unveils ML Chip with Nearly 1,100 RISC-V Cores

December 8, 2020

At the RISC-V Summit today, Art Swift, CEO of Esperanto Technologies, announced a new, RISC-V based chip aimed at machine learning and containing nearly 1,100 low-power cores based on the open-source RISC-V architecture. Esperanto Technologies, headquartered in... Read more…

By Oliver Peckham

Azure Scaled to Record 86,400 Cores for Molecular Dynamics

November 20, 2020

A new record for HPC scaling on the public cloud has been achieved on Microsoft Azure. Led by Dr. Jer-Ming Chia, the cloud provider partnered with the Beckman I Read more…

By Oliver Peckham

NICS Unleashes ‘Kraken’ Supercomputer

April 4, 2008

A Cray XT4 supercomputer, dubbed Kraken, is scheduled to come online in mid-summer at the National Institute for Computational Sciences (NICS). The soon-to-be petascale system, and the resulting NICS organization, are the result of an NSF Track II award of $65 million to the University of Tennessee and its partners to provide next-generation supercomputing for the nation's science community. Read more…

Is the Nvidia A100 GPU Performance Worth a Hardware Upgrade?

October 16, 2020

Over the last decade, accelerators have seen an increasing rate of adoption in high-performance computing (HPC) platforms, and in the June 2020 Top500 list, eig Read more…

By Hartwig Anzt, Ahmad Abdelfattah and Jack Dongarra

Aurora’s Troubles Move Frontier into Pole Exascale Position

October 1, 2020

Intel’s 7nm node delay has raised questions about the status of the Aurora supercomputer that was scheduled to be stood up at Argonne National Laboratory next year. Aurora was in the running to be the United States’ first exascale supercomputer although it was on a contemporaneous timeline with... Read more…

By Tiffany Trader

Google Hires Longtime Intel Exec Bill Magro to Lead HPC Strategy

September 18, 2020

In a sign of the times, another prominent HPCer has made a move to a hyperscaler. Longtime Intel executive Bill Magro joined Google as chief technologist for hi Read more…

By Tiffany Trader

Julia Update: Adoption Keeps Climbing; Is It a Python Challenger?

January 13, 2021

The rapid adoption of Julia, the open source, high level programing language with roots at MIT, shows no sign of slowing according to data from Julialang.org. I Read more…

By John Russell

10nm, 7nm, 5nm…. Should the Chip Nanometer Metric Be Replaced?

June 1, 2020

The biggest cool factor in server chips is the nanometer. AMD beating Intel to a CPU built on a 7nm process node* – with 5nm and 3nm on the way – has been i Read more…

By Doug Black

Leading Solution Providers

Contributors

Programming the Soon-to-Be World’s Fastest Supercomputer, Frontier

January 5, 2021

What’s it like designing an app for the world’s fastest supercomputer, set to come online in the United States in 2021? The University of Delaware’s Sunita Chandrasekaran is leading an elite international team in just that task. Chandrasekaran, assistant professor of computer and information sciences, recently was named... Read more…

By Tracey Bryant

Top500: Fugaku Keeps Crown, Nvidia’s Selene Climbs to #5

November 16, 2020

With the publication of the 56th Top500 list today from SC20's virtual proceedings, Japan's Fugaku supercomputer – now fully deployed – notches another win, Read more…

By Tiffany Trader

European Commission Declares €8 Billion Investment in Supercomputing

September 18, 2020

Just under two years ago, the European Commission formalized the EuroHPC Joint Undertaking (JU): a concerted HPC effort (comprising 32 participating states at c Read more…

By Oliver Peckham

Texas A&M Announces Flagship ‘Grace’ Supercomputer

November 9, 2020

Texas A&M University has announced its next flagship system: Grace. The new supercomputer, named for legendary programming pioneer Grace Hopper, is replacing the Ada system (itself named for mathematician Ada Lovelace) as the primary workhorse for Texas A&M’s High Performance Research Computing (HPRC). Read more…

By Oliver Peckham

At Oak Ridge, ‘End of Life’ Sometimes Isn’t

October 31, 2020

Sometimes, the old dog actually does go live on a farm. HPC systems are often cursed with short lifespans, as they are continually supplanted by the latest and Read more…

By Oliver Peckham

Nvidia and EuroHPC Team for Four Supercomputers, Including Massive ‘Leonardo’ System

October 15, 2020

The EuroHPC Joint Undertaking (JU) serves as Europe’s concerted supercomputing play, currently comprising 32 member states and billions of euros in funding. I Read more…

By Oliver Peckham

Gordon Bell Special Prize Goes to Massive SARS-CoV-2 Simulations

November 19, 2020

2020 has proven a harrowing year – but it has produced remarkable heroes. To that end, this year, the Association for Computing Machinery (ACM) introduced the Read more…

By Oliver Peckham

Nvidia-Arm Deal a Boon for RISC-V?

October 26, 2020

The $40 billion blockbuster acquisition deal that will bring chipmaker Arm into the Nvidia corporate family could provide a boost for the competing RISC-V architecture. As regulators in the U.S., China and the European Union begin scrutinizing the impact of the blockbuster deal on semiconductor industry competition and innovation, the deal has at the very least... Read more…

By George Leopold

  • arrow
  • Click Here for More Headlines
  • arrow
Do NOT follow this link or you will be banned from the site!
Share This