False Sharing and Padding is the final installment of a 3-part educational series on Optimization Techniques for the Intel® MIC Architecture by Colfax Research. The series focuses on select topics on optimization of applications for Intel’s multi-core and manycore architectures (Intel® Xeon® processors and Intel® Xeon Phi™ processors).
In False Sharing and Padding, the authors discuss false sharing, highlighting the situations in which it may occur, and eliminating it with the help of data container padding. For a practical illustration, they construct and optimize a micro-kernel for binning particles based on their coordinates. Similar workloads occur in Monte Carlos simulations, particle physics software, and statistical analysis. Results show that the impact of false sharing may be as high as an order of magnitude performance loss in a parallel application. On Intel Xeon processors, padding required to eliminate false sharing is greater than on Intel Xeon Phi coprocessors, so target-specific padding values may be used in real-life applications.
Read Part 3 of the series on False Sharing and Padding >
Access Part 1: Multi-Threading and Parallel Reduction >
Access Part 2: Strip-Mining for Vectorization >