PNNL Launches Center for Advanced Technology Evaluation

By John Russell

November 13, 2015

With the recent launch of the Center for Advanced Technology Evaluation (CENATE), Pacific Northwest National Laboratory is well positioned to serve as a nexus for evaluating technologies that will be foundational for extreme-scale systems – all within a first-of-its-kind computing proving ground. Funded by the Department of Energy Office of Advanced Scientific Computing Research, CENATE’s mission is to deliver concrete benefits to PNNL and to the broader technology research community.

The idea is straightforward: By creating a focal point for the evaluation of early systems technologies that too often are conducted between isolated research teams and technology providers, CENATE provides a needed research and development connection function. The intent is to productively impact the major advancements needed in computing technology and energy efficiency in the transition to exascale and beyond.

“It will be essential to engage a hierarchy of strategic partnerships and integrated methodologies to accelerate both numerically and data-intensive breakthrough technologies toward efficient, productive, high-end computing,” said DOE-ASCR Research Division Director William Harrod. “CENATE’s entire operations model speaks directly to this.” PNNL opened CENATE in mid October and will be spreading the CENATE message as part of a contingent of national laboratories at the DOE booth at SC15 next week.

CENATE is a natural progression of activities within PNNL’s Performance and Architecture Lab (PAL). In the last few years, PNNL used internal investments to create a state-of-the-art measurement facility. The laboratory affords accurate measurements of performance, power, and thermal effects, from device to system level. PAL has also developed methods and tools for modeling and simulating performance and power; researchers will be able to the infrastructure and tools to gain deeper insight into system and application performance and, hopefully, an improved ability ‘to design ahead.’

“Application workloads and technologies under investigation will cover many scientific domains of interest to the DOE,” said Adolfy Hoisie, PNNL’s chief scientist for computing and CENATE’s principal investigator and director. “CENATE facilities will be made available to the DOE laboratory community, and our findings will be disseminated among the DOE complex and to technology provider communities within NDA and IP limitations. Moreover, we will make the most of our industry connections to provide added technology evaluation capabilities, including early access to technologies, equipment, and knowledge resources.”

CENATE_graphicsThe CENATE Resource
CENATE is designed to provide a multi-perspective, integrated approach in its evaluation process, undertaking empirical analyses affecting sub-system or constituent components to full nodes and small clusters with network switches that are fully populated with compute nodes. Sub-systems of interest include the processor socket (homogeneous and accelerated systems), memories (dynamic, static, memory cubes), motherboards, networks (network interface cards and switches), and input/output and storage devices.

The CENATE core encompasses instrumentation, testbeds, evaluation, and modeling and simulation research areas that primarily will focus on workload applications of interest to DOE with the notion that the broader high-performance computing community can take advantage of synergies as they develop. Hosie emphasized the specifichow, when, and what type of evaluation mechanism’ employed in the CENATE pipeline will depend completely on where the technology of interest is in its life cycle.

“Within CENATE, we can take a concept, an early idea where a hardware prototype doesn’t exist and employ modeling and simulation,” he said. “At another stage of the technology development pipeline, very early technologies may be available for measurement in the Advanced Measurement Lab at device level, such as 7nm technology. At another stage of technology maturity a subsystem such as a novel memory board would be available for measurements in AML.”

In both cases – from early measurements to assessment of the impact of such technologies on DOE applications, systems, and power performance – research will be conducted using PAL’s modeling and simulation bag of tools. This measure-model-design pipeline is just one of many potential options that CENATE capabilities afford for steering future system designs and application mapping for optimal performance under the constraints of power consumption.

Tools to Grow By
Measurement instrumentation will provide detailed power information facilitated by PNNL’s investments in technical capabilities that already include the AML. These dedicated physical labs will enable rapid evaluations of component technologies, while evaluations at small and medium scales will feed the analysis pipeline toward modeling and simulation to assess the impact of technologies at large-scale and explore how the technologies may evolve in subsequent generations.

The testbed infrastructure features numerous workbenches—with room for more—that accommodate black box, or complete systems, with standard I/O devices, network connections, and external power meters that can be evaluated in a relatively short turnaround. In addition, there are open-box, or white box, systems where carrier boards are exposed and only include the essentials, such as CPUs, memory, and storage. These systems require a longer setup but also provide added power evaluation via external digital-to-analog converters and voltage probes. CENATE also can manage gray box, or single-component, evaluations that require specific carrier boards and coarse power instrumentation to examine. Gray box evaluation times will vary by system.

“CENATE will assist in preparing applications for future technology generations by assessing the importance of components and their impact on large-scale system deployments still on the horizon,” said Darren Kerbyson, CENATE’s lead scientist. “Ultimately, our evaluations and prediction processes will weed out robustness issues associated with early hardware that can be an imposing barrier en route to production.”

CENATE_graphicsCENATE leverages PNNL’s existing expertise in analytical modeling of performance and power of large-scale applications and systems, as well as work on adapting open-source, near-cycle-accurate system simulations for small scales. Hoisie and Kerbyson manage the center, and the evaluation area leads include Roberto Gioiosa, Instrumentation; Andres Marquez, Testbeds (scalability and new technology); Nathan Tallent, Evaluation; and Kevin Barker, Modeling and Simulation.

“To enable extreme-scale science and computing, especially as defined by DOE-ASCR, we need viable methods for more effectively examining the applications that pave the way to the new state of the art,” Hoisie said. “These evaluations also must provide accessible feedback in the form of useful data about performance and energy efficiencies. These data then will be employed to refine technology using co-design methods and additional optimizations. CENATE is a clear bridge that also aligns well with the current Executive Order for the National Strategic Computing Initiative.”
Browse News From SC15The long-term goal is for CENATE to get deeply enmeshed in the many computing projects funded by DOE for exascale and beyond. To that end, CENATE facilities will be made available to the DOE laboratory community via an instrument-like resource and time allocation to assure broad connectivity. A Wiki is already in development to facilitate rapid dissemination of results, within the confines of non-disclosure and intellectual property agreements with industry partners, as well as to provide a users’ forum for observations, suggestions, and general comments. Workshops, webinars, and onsite host visitors, all aimed at developing new testing methods and procedures, will further promote interaction and augment CENATE general expertise through contributions from experts within the HPC scientific community.

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

GlobalFoundries Puts Wind in AMD’s Sails with 12nm FinFET

September 24, 2017

From its annual tech conference last week (Sept. 13), where GlobalFoundries welcomed more than 600 semiconductor professionals (reaching the Santa Clara venue’s max capacity and doubling 2016 attendee numbers), the one Read more…

By Tiffany Trader

Machine Learning at HPC User Forum: Drilling into Specific Use Cases

September 22, 2017

The 66th HPC User Forum held September 5-7, in Milwaukee, Wisconsin, at the elegant and historic Pfister Hotel, highlighting the 1893 Victorian décor and art of “The Grand Hotel Of The West,” contrasted nicely with Read more…

By Arno Kolster

Google Cloud Makes Good on Promise to Add Nvidia P100 GPUs

September 21, 2017

Google has taken down the notice on its cloud platform website that says Nvidia Tesla P100s are “coming soon.” That's because the search giant has announced the beta launch of the high-end P100 Nvidia Tesla GPUs on t Read more…

By George Leopold

HPE Extreme Performance Solutions

HPE Prepares Customers for Success with the HPC Software Portfolio

High performance computing (HPC) software is key to harnessing the full power of HPC environments. Development and management tools enable IT departments to streamline installation and maintenance of their systems as well as create, optimize, and run their HPC applications. Read more…

Cray Wins $48M Supercomputer Contract from KISTI

September 21, 2017

It was a good day for Cray which won a $48 million contract from the Korea Institute of Science and Technology Information (KISTI) for a 128-rack CS500 cluster supercomputer. The new system, equipped with Intel Xeon Scal Read more…

By John Russell

GlobalFoundries Puts Wind in AMD’s Sails with 12nm FinFET

September 24, 2017

From its annual tech conference last week (Sept. 13), where GlobalFoundries welcomed more than 600 semiconductor professionals (reaching the Santa Clara venue Read more…

By Tiffany Trader

Machine Learning at HPC User Forum: Drilling into Specific Use Cases

September 22, 2017

The 66th HPC User Forum held September 5-7, in Milwaukee, Wisconsin, at the elegant and historic Pfister Hotel, highlighting the 1893 Victorian décor and art o Read more…

By Arno Kolster

Stanford University and UberCloud Achieve Breakthrough in Living Heart Simulations

September 21, 2017

Cardiac arrhythmia can be an undesirable and potentially lethal side effect of drugs. During this condition, the electrical activity of the heart turns chaotic, Read more…

By Wolfgang Gentzsch, UberCloud, and Francisco Sahli, Stanford University

PNNL’s Center for Advanced Tech Evaluation Seeks Wider HPC Community Ties

September 21, 2017

Two years ago the Department of Energy established the Center for Advanced Technology Evaluation (CENATE) at Pacific Northwest National Laboratory (PNNL). CENAT Read more…

By John Russell

Exascale Computing Project Names Doug Kothe as Director

September 20, 2017

The Department of Energy’s Exascale Computing Project (ECP) has named Doug Kothe as its new director effective October 1. He replaces Paul Messina, who is stepping down after two years to return to Argonne National Laboratory. Kothe is a 32-year veteran of DOE’s National Laboratory System. Read more…

Takeaways from the Milwaukee HPC User Forum

September 19, 2017

Milwaukee’s elegant Pfister Hotel hosted approximately 100 attendees for the 66th HPC User Forum (September 5-7, 2017). In the original home city of Pabst Blu Read more…

By Merle Giles

Kathy Yelick Charts the Promise and Progress of Exascale Science

September 15, 2017

On Friday, Sept. 8, Kathy Yelick of Lawrence Berkeley National Laboratory and the University of California, Berkeley, delivered the keynote address on “Breakthrough Science at the Exascale” at the ACM Europe Conference in Barcelona. In conjunction with her presentation, Yelick agreed to a short Q&A discussion with HPCwire. Read more…

By Tiffany Trader

DARPA Pledges Another $300 Million for Post-Moore’s Readiness

September 14, 2017

The Defense Advanced Research Projects Agency (DARPA) launched a giant funding effort to ensure the United States can sustain the pace of electronic innovation vital to both a flourishing economy and a secure military. Under the banner of the Electronics Resurgence Initiative (ERI), some $500-$800 million will be invested in post-Moore’s Law technologies. Read more…

By Tiffany Trader

How ‘Knights Mill’ Gets Its Deep Learning Flops

June 22, 2017

Intel, the subject of much speculation regarding the delayed, rewritten or potentially canceled “Aurora” contract (the Argonne Lab part of the CORAL “ Read more…

By Tiffany Trader

Reinders: “AVX-512 May Be a Hidden Gem” in Intel Xeon Scalable Processors

June 29, 2017

Imagine if we could use vector processing on something other than just floating point problems.  Today, GPUs and CPUs work tirelessly to accelerate algorithms Read more…

By James Reinders

NERSC Scales Scientific Deep Learning to 15 Petaflops

August 28, 2017

A collaborative effort between Intel, NERSC and Stanford has delivered the first 15-petaflops deep learning software running on HPC platforms and is, according Read more…

By Rob Farber

Oracle Layoffs Reportedly Hit SPARC and Solaris Hard

September 7, 2017

Oracle’s latest layoffs have many wondering if this is the end of the line for the SPARC processor and Solaris OS development. As reported by multiple sources Read more…

By John Russell

Six Exascale PathForward Vendors Selected; DoE Providing $258M

June 15, 2017

The much-anticipated PathForward awards for hardware R&D in support of the Exascale Computing Project were announced today with six vendors selected – AMD Read more…

By John Russell

Top500 Results: Latest List Trends and What’s in Store

June 19, 2017

Greetings from Frankfurt and the 2017 International Supercomputing Conference where the latest Top500 list has just been revealed. Although there were no major Read more…

By Tiffany Trader

IBM Clears Path to 5nm with Silicon Nanosheets

June 5, 2017

Two years since announcing the industry’s first 7nm node test chip, IBM and its research alliance partners GlobalFoundries and Samsung have developed a proces Read more…

By Tiffany Trader

Nvidia Responds to Google TPU Benchmarking

April 10, 2017

Nvidia highlights strengths of its newest GPU silicon in response to Google's report on the performance and energy advantages of its custom tensor processor. Read more…

By Tiffany Trader

Leading Solution Providers

Graphcore Readies Launch of 16nm Colossus-IPU Chip

July 20, 2017

A second $30 million funding round for U.K. AI chip developer Graphcore sets up the company to go to market with its “intelligent processing unit” (IPU) in Read more…

By Tiffany Trader

Google Releases Deeplearn.js to Further Democratize Machine Learning

August 17, 2017

Spreading the use of machine learning tools is one of the goals of Google’s PAIR (People + AI Research) initiative, which was introduced in early July. Last w Read more…

By John Russell

Russian Researchers Claim First Quantum-Safe Blockchain

May 25, 2017

The Russian Quantum Center today announced it has overcome the threat of quantum cryptography by creating the first quantum-safe blockchain, securing cryptocurrencies like Bitcoin, along with classified government communications and other sensitive digital transfers. Read more…

By Doug Black

EU Funds 20 Million Euro ARM+FPGA Exascale Project

September 7, 2017

At the Barcelona Supercomputer Centre on Wednesday (Sept. 6), 16 partners gathered to launch the EuroEXA project, which invests €20 million over three-and-a-half years into exascale-focused research and development. Led by the Horizon 2020 program, EuroEXA picks up the banner of a triad of partner projects — ExaNeSt, EcoScale and ExaNoDe — building on their work... Read more…

By Tiffany Trader

Google Debuts TPU v2 and will Add to Google Cloud

May 25, 2017

Not long after stirring attention in the deep learning/AI community by revealing the details of its Tensor Processing Unit (TPU), Google last week announced the Read more…

By John Russell

Amazon Debuts New AMD-based GPU Instances for Graphics Acceleration

September 12, 2017

Last week Amazon Web Services (AWS) streaming service, AppStream 2.0, introduced a new GPU instance called Graphics Design intended to accelerate graphics. The Read more…

By John Russell

Cray Moves to Acquire the Seagate ClusterStor Line

July 28, 2017

This week Cray announced that it is picking up Seagate's ClusterStor HPC storage array business for an undisclosed sum. "In short we're effectively transitioning the bulk of the ClusterStor product line to Cray," said CEO Peter Ungaro. Read more…

By Tiffany Trader

GlobalFoundries: 7nm Chips Coming in 2018, EUV in 2019

June 13, 2017

GlobalFoundries has formally announced that its 7nm technology is ready for customer engagement with product tape outs expected for the first half of 2018. The Read more…

By Tiffany Trader

  • arrow
  • Click Here for More Headlines
  • arrow
Share This