A Conversation with James Reinders

By Tiffany Trader and John Russell

January 21, 2016

As Chief Evangelist of Intel Software Products, James Reinders spends most of his working hours thinking about and promoting parallel programming. He’s essentially a professor at large, attuning himself to the needs of software developers with an interest in parallel programming so he can offer guidance on techniques, ways of learning, and ways to “think parallel” – all with a strong Intel bent, naturally.

As Intel moved from a multicore paradigm to a manycore one with the introduction of Xeon Phi in 2010, Reinders’ parallel programming evangelizing went into overdrive. In the next half-decade, Reinders and Intel colleague Jim Jeffers co-authored two books focused on demonstrating the computational potential of Phi’s 60+ cores: High Performance Parallelism Pearls volume 1 and 2. With the second-generation Phi, Knights Landing, on-deck for general availability in 2016, we spoke with Reinders about the implications of Intel’s design choices for Knights Landing, what that means for compatibility and performance and what the user community can do to get ready for the first self-hosted manycore Xeon. Read the first half of our in-depth interview below.

HPCwire: How are the various communities and stakeholders preparing for Knights Landing? Can you talk about the challenges relating to porting and exploiting parallelism?

James Reinders: One of the things that distinguishes Xeon Phi is it’s not challenging to port to at all. Being on a coprocessor or PCI card requires a lot of considerations because of the limitations in the size of memory and having to stage your algorithms and so forth. Anytime you are trying to target something that sits on a PCI card, you have a challenge, and we really felt that with Xeon Phi, but one of the huge design principles behind Xeon Phi that we’ve delivered very well on is there is no porting effort per se to Xeon Phi because it essentially looks like a very high-core count Xeon. So the porting is the easy part for Knights Landing since it will be a processor and not sitting on a coprocessor card — unless you design to buy it that way.

As a processor, we’ve gotten rid of what I would say is the number one headache with Xeon Phi, which is the coprocessor, and you’re not left with a porting challenge, you’re left with a challenge of scaling your application. You’re going to face that with any processor or any compute device of any sort. So that’s why we spent so much energy focused on evangelist work, teaching and code modernization. The real challenge for the entire industry for parallel programming is finding and exploiting parallelism, regardless of what compute device you want to use. And I think with Xeon Phi what we’ve done is eliminate the porting issues and purely made it an issue of parallel programming.

HPCwire: Is one potential downside of the manycore processor approach in contrast with the accelerator or coprocessor paradigm that there are no full-strength cores to handle the parts of the code that don’t parallelize?

Reinders: You’re referring to Amdahl’s law, where the part of your program that’s serial is going to have a performance challenge. So you get bottlenecks around that. Anytime you have a system that has something highly parallel in it and you use that to speed up your parallel code, when you fall back to doing serial code, you’ve got a challenge. On Knights Corner, because it was a coprocessor, you try to divide your program between the coprocessor that’s highly parallel and your host, which is probably a very capable Xeon. So it is helpful to have a very capable host processor in that case. You’re not going to want to run something fast, accelerate it and have a weak processor coupled with it. For Knights Landing, we have much stronger serial performance than Knights Corner — and that’s on purpose.

If you take a look at Knights Corner, we have 61 cores and the performance difference between a Knights Corner core and a Xeon core is give or take 10X. Some people might tell you it’s 12 or 14X; it depends on the application — but it’s pretty severe. That means you really want to avoid having a lot of serial code run on the Knights Corner. It was pretty bad gap, owing to Amdahl’s effect. A well-parallelized program worked great; one that had serial regions had trouble.

On Knights Landing, we’ve reduced that to about a 3X difference. Of course, the only way to reduce this to a 1X is to become a Xeon. But that’s not the point of Xeon Phi, the point is to scale higher. But the fact that we’re at 3X, we’re seeing really good results with that, meaning that a system built with just Knights Landing as processors works pretty darn well.

HPCwire: Sounds like a balancing act.

Reinders: When you step back and look at computer architecture, there’s a lot of fun knobs you can turn when you are designing a machine and that’s what we as engineers do: we’re turning knobs. There are two main ones. One is big versus little cores, so when you go to a littler core, you can have more of them and you can scale further. But if you make them bigger, you can’t scale as much but you can handle a wider variety of code. We’ve turned that – that’s one knob.

Another knob you can turn is compatibility. If you take a look at a GPU design, including Intel’s GPUs, one of the design things you do is require a lot of the parallelism is to be done in lock-step, meaning the individual processing capabilities cannot do different code; they have to run exactly the same code at the same time. That has its pros and cons too. So for Xeon and Xeon Phi, we’ve made a very tight relationship between them in terms of compatibility. That’s our design decision. It has a lot of advantages and gives us the ability for Xeon Phi to scale higher than Xeon but to require that you are doing parallel programming. If you go and try to program our GPUs, you will find you don’t have that capability and are much more restricted in the programs you can run, and that gives the GPU certain capabilities that are useful for graphics units.

Compatibility with a processor also means an enormous amount of flexibility — which provides a large degree of preservation for code investment. Your code can keep working; you can decide how much to invest for performance, but you don’t have to go make the change in it just because you changed hardware generations.

HPCwire: Could you provide examples of codes that are best suited for Knights Landing and those that are not as well-suited?

Reinders: The one thing about Knights Landing is that it’s highly-parallel, so the Amdahl’s effect becomes a key consideration. So if your program is not parallel or not spending a significant amount of time doing things in parallel, then Knights Landing is not likely to be interesting.

There is an exception to that due to the aggregate bandwidth on Xeon Phi being higher than on Xeon, so we have seen some examples of codes that lean pretty high on bandwidth that see benefits on Xeon Phi even though that they aren’t as parallel as you might think. Because if your processor is waiting for bandwidth, feeding it more bandwidth can be helpful. Because aggregate bandwidth is high on Xeon Phi – it always has been – and you add in the high-bandwidth memory on Knights Landing, there are some applications that are a little less parallel than you’d expect that can get a boost on Knights Landing, but for the most part you are looking at programs that are parallel. So in the HPC domain, everything — that’s the easy part. Everything is a good target on Knights Landing but that’s simply because the HPC world has been parallel for so long that to be a successful code in HPC you need to be parallel. Outside of HPC, it’s less clear. There are certainly things in technical computing that might be outside what people call traditional HPC, and Knights Landing looks very good on the ones that are parallel there, including big data problems and machine learning. Now whether you consider these to be HPC, to me it’s kind of fuzzy.

HPCwire: Speaking of machine learning – do you expect the Knights Landing will get traction for neural networks?

Reinders: It’s quite a good device for the different neural nets both the training and the usage of them. Knights Landing in particular has some great attributes there. Because it’s not a coprocessor, we can talk about having large amounts of memory on it, which can be a huge advantage to many science problems and machine learning as well. That’s going to be an interesting thing to understand how to properly represent because you can choose your benchmarks carefully to fit in a small or select amount of memory, but a lot of times, with users, if their programs haven’t been as well conditioned, it would take effort if it’s even possible to condition an algorithm or application to run in too tight of a piece of memory. When you’re talking about a processor, like Knights Landing, that has a large amount of memory capability, you can build machines with an appropriate size of memory to fit your application, you’re not straddled by what happens to fit on a coprocessor code, which with KNC was a challenge for us sometimes. That constraint of more limited memory definitely limits some of the applications or algorithms you can run, including machine learning.

HPCwire: What can prospective Knights Landing users, most of whom do not yet have access to test systems or test systems of scale, do to prepare their codes?

Reinders: There are three keys for parallel programming: getting the program to scale, getting it to vectorize, and understanding data locality. With regard to vectorization and data locality, I’ve found there are a lot of machines out there that people can do their work on. Whether you’ve structured your code to vectorize or to be well-conditioned in memory, you can pick pretty much any Xeon or probably any other machine based on processors and you can focus on whether you’ve done the right things so that a compiler can do something for you there. I’d probably recommend a Xeon because then you are using an Intel compiler and if you are trying to see if it vectorizes, you are matched with the capabilities of the same compiler.

Scaling’s a more difficult one. Some people will ask me: can you just run on a high core-count Xeon? In my experience, it’s better if you run on a Knights Corner because you have 61 cores. Most people with Xeons tend to have machines that run up to 8 or 10 cores. As soon as I’ve said that someone holds their hand up and says they have access to a dual-socket 18-core Haswell machine. That’ll do just fine, although the price tag on that is a little bit higher than a Knights Corner card, but I’ll leave that to you to determine.

What I’ve found is — if you look at whether you scale well on 4 and 8 cores, you probably haven’t done the in-depth look to understand whether you’ve exposed enough parallelism to scale higher.

This is one of the two-edged swords we have with our programming techniques because we’re so compatible with Xeon that you don’t need to scale perfectly to run on a Xeon Phi. You do to get great performance, but you don’t have to do that. Whereas if you’re programming for a GPU, you need to decompose your problem in a way that scales; it’s just not possible to run there otherwise. It’s a different mode of thought and I think sometimes it’s tripped people up. They port code quickly to Xeon Phi and they’re not being forced to make their program scale. So the short answer here is you need to go force yourself to do something to scale your code. Figure out why it’s not scaling if it’s not. Fortunately, we have tools that can help in Parallel Studio and so forth, but there’s no substitute for that.

So as far as getting prepared, those are the mechanical things. Worry about scaling; worry about vectorization; worry about data locality. All three of those things can be a challenge and it’s a lot to think about, but there’s some great tools and different ways to learn. But I keep getting reminded by things that affect me in interfacing with customers that nothing’s more important than this catch phrase I use: “think parallel.” I could spend a lot of time describing what that means, but there’s no substitute as a programmer for really understanding where the parallelism is. Sometimes I run into examples where someone’s dove in a little too quickly and they’re trying to get their program to scale or trying to get an existing program to vectorize, and they haven’t stepped back, taken a deep breath, and thought about “where the heck is my parallelism.” Maybe they should think of the problem a little differently, structure the algorithm differently – that’s your most powerful tool. Instead of going and studying OpenMP, or CUDA or OpenCL or TBB, it’s useful to step back and study parallel programming as a general topic – the algorithms that work, understand what stencils are, understand what MapReduce means. Sometimes, when I’m talking to people who ask for advice, I’ll probe them and if they don’t know [these more basic elements], my strongest advice is to go learn these things before you start sprinkling in OpenMP commands; but if you already know these things, then the answer is to get your code to scale and vectorize.

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

UCSD, AIST Forge Tighter Alliance with AI-Focused MOU

January 18, 2018

The rich history of collaboration between UC San Diego and AIST in Japan is getting richer. The organizations entered into a five-year memorandum of understanding on January 10. The MOU represents the continuation of a 1 Read more…

By Tiffany Trader

New Blueprint for Converging HPC, Big Data

January 18, 2018

After five annual workshops on Big Data and Extreme-Scale Computing (BDEC), a group of international HPC heavyweights including Jack Dongarra (University of Tennessee), Satoshi Matsuoka (Tokyo Institute of Technology), Read more…

By John Russell

Researchers Measure Impact of ‘Meltdown’ and ‘Spectre’ Patches on HPC Workloads

January 17, 2018

Computer scientists from the Center for Computational Research, State University of New York (SUNY), University at Buffalo have examined the effect of Meltdown and Spectre security updates on the performance of popular H Read more…

By Tiffany Trader

HPE Extreme Performance Solutions

HPE and NREL Take Steps to Create a Sustainable, Energy-Efficient Data Center with an H2 Fuel Cell

As enterprises attempt to manage rising volumes of data, unplanned data center outages are becoming more common and more expensive. As the cost of downtime rises, enterprises lose out on productivity and valuable competitive advantage without access to their critical data. Read more…

Fostering Lustre Advancement Through Development and Contributions

January 17, 2018

Six months after organizational changes at Intel's High Performance Data (HPDD) division, most in the Lustre community have shed any initial apprehension around the potential changes that could affect or disrupt Lustre Read more…

By Carlos Aoki Thomaz

UCSD, AIST Forge Tighter Alliance with AI-Focused MOU

January 18, 2018

The rich history of collaboration between UC San Diego and AIST in Japan is getting richer. The organizations entered into a five-year memorandum of understandi Read more…

By Tiffany Trader

New Blueprint for Converging HPC, Big Data

January 18, 2018

After five annual workshops on Big Data and Extreme-Scale Computing (BDEC), a group of international HPC heavyweights including Jack Dongarra (University of Te Read more…

By John Russell

Researchers Measure Impact of ‘Meltdown’ and ‘Spectre’ Patches on HPC Workloads

January 17, 2018

Computer scientists from the Center for Computational Research, State University of New York (SUNY), University at Buffalo have examined the effect of Meltdown Read more…

By Tiffany Trader

Fostering Lustre Advancement Through Development and Contributions

January 17, 2018

Six months after organizational changes at Intel's High Performance Data (HPDD) division, most in the Lustre community have shed any initial apprehension aroun Read more…

By Carlos Aoki Thomaz

When the Chips Are Down

January 11, 2018

In the last article, "The High Stakes Semiconductor Game that Drives HPC Diversity," I alluded to the challenges facing the semiconductor industry and how that may impact the evolution of HPC systems over the next few years. I thought I’d lift the covers a little and look at some of the commercial challenges that impact the component technology we use in HPC. Read more…

By Dairsie Latimer

How Meltdown and Spectre Patches Will Affect HPC Workloads

January 10, 2018

There have been claims that the fixes for the Meltdown and Spectre security vulnerabilities, named the KPTI (aka KAISER) patches, are going to affect applicatio Read more…

By Rosemary Francis

Momentum Builds for US Exascale

January 9, 2018

2018 looks to be a great year for the U.S. exascale program. The last several months of 2017 revealed a number of important developments that help put the U.S. Read more…

By Alex R. Larzelere

ANL’s Rick Stevens on CANDLE, ARM, Quantum, and More

January 8, 2018

Late last year HPCwire caught up with Rick Stevens, associate laboratory director for computing, environment and life Sciences at Argonne National Laboratory, f Read more…

By John Russell

Inventor Claims to Have Solved Floating Point Error Problem

January 17, 2018

"The decades-old floating point error problem has been solved," proclaims a press release from inventor Alan Jorgensen. The computer scientist has filed for and Read more…

By Tiffany Trader

US Coalesces Plans for First Exascale Supercomputer: Aurora in 2021

September 27, 2017

At the Advanced Scientific Computing Advisory Committee (ASCAC) meeting, in Arlington, Va., yesterday (Sept. 26), it was revealed that the "Aurora" supercompute Read more…

By Tiffany Trader

Japan Unveils Quantum Neural Network

November 22, 2017

The U.S. and China are leading the race toward productive quantum computing, but it's early enough that ultimate leadership is still something of an open questi Read more…

By Tiffany Trader

AMD Showcases Growing Portfolio of EPYC and Radeon-based Systems at SC17

November 13, 2017

AMD’s charge back into HPC and the datacenter is on full display at SC17. Having launched the EPYC processor line in June along with its MI25 GPU the focus he Read more…

By John Russell

Nvidia Responds to Google TPU Benchmarking

April 10, 2017

Nvidia highlights strengths of its newest GPU silicon in response to Google's report on the performance and energy advantages of its custom tensor processor. Read more…

By Tiffany Trader

IBM Begins Power9 Rollout with Backing from DOE, Google

December 6, 2017

After over a year of buildup, IBM is unveiling its first Power9 system based on the same architecture as the Department of Energy CORAL supercomputers, Summit a Read more…

By Tiffany Trader

Fast Forward: Five HPC Predictions for 2018

December 21, 2017

What’s on your list of high (and low) lights for 2017? Volta 100’s arrival on the heels of the P100? Appearance, albeit late in the year, of IBM’s Power9? Read more…

By John Russell

Chip Flaws ‘Meltdown’ and ‘Spectre’ Loom Large

January 4, 2018

The HPC and wider tech community have been abuzz this week over the discovery of critical design flaws that impact virtually all contemporary microprocessors. T Read more…

By Tiffany Trader

Leading Solution Providers

Perspective: What Really Happened at SC17?

November 22, 2017

SC is over. Now comes the myriad of follow-ups. Inboxes are filled with templated emails from vendors and other exhibitors hoping to win a place in the post-SC thinking of booth visitors. Attendees of tutorials, workshops and other technical sessions will be inundated with requests for feedback. Read more…

By Andrew Jones

Tensors Come of Age: Why the AI Revolution Will Help HPC

November 13, 2017

Thirty years ago, parallel computing was coming of age. A bitter battle began between stalwart vector computing supporters and advocates of various approaches to parallel computing. IBM skeptic Alan Karp, reacting to announcements of nCUBE’s 1024-microprocessor system and Thinking Machines’ 65,536-element array, made a public $100 wager that no one could get a parallel speedup of over 200 on real HPC workloads. Read more…

By John Gustafson & Lenore Mullin

Delays, Smoke, Records & Markets – A Candid Conversation with Cray CEO Peter Ungaro

October 5, 2017

Earlier this month, Tom Tabor, publisher of HPCwire and I had a very personal conversation with Cray CEO Peter Ungaro. Cray has been on something of a Cinderell Read more…

By Tiffany Trader & Tom Tabor

Flipping the Flops and Reading the Top500 Tea Leaves

November 13, 2017

The 50th edition of the Top500 list, the biannual publication of the world’s fastest supercomputers based on public Linpack benchmarking results, was released Read more…

By Tiffany Trader

GlobalFoundries, Ayar Labs Team Up to Commercialize Optical I/O

December 4, 2017

GlobalFoundries (GF) and Ayar Labs, a startup focused on using light, instead of electricity, to transfer data between chips, today announced they've entered in Read more…

By Tiffany Trader

How Meltdown and Spectre Patches Will Affect HPC Workloads

January 10, 2018

There have been claims that the fixes for the Meltdown and Spectre security vulnerabilities, named the KPTI (aka KAISER) patches, are going to affect applicatio Read more…

By Rosemary Francis

HPC Chips – A Veritable Smorgasbord?

October 10, 2017

For the first time since AMD's ill-fated launch of Bulldozer the answer to the question, 'Which CPU will be in my next HPC system?' doesn't have to be 'Whichever variety of Intel Xeon E5 they are selling when we procure'. Read more…

By Dairsie Latimer

Nvidia, Partners Announce Several V100 Servers

September 27, 2017

Here come the Volta 100-based servers. Nvidia today announced an impressive line-up of servers from major partners – Dell EMC, Hewlett Packard Enterprise, IBM Read more…

By John Russell

  • arrow
  • Click Here for More Headlines
  • arrow
Share This