Light-enabled Microprocessor Holds Promise for Faster Computers

By John Russell

February 23, 2016

Combining electronics and photonics on semiconductor microchips to speed data transmission isn’t a new idea – the potential for better performance and power reduction are enticing. However thorny manufacturing issues have so far limited widespread use of this approach. That could change soon according to a recent report in Nature[i] and would have have broad implications extending even to efforts to achieve exascale computing, say the authors.

In the paper – “Single-chip microprocessor that communicates directly using light” – researchers from UC Berkeley, University of Colorado, and MIT report fabricating an electronic–photonic system on a single chip integrating over 70 million transistors and 850 photonic components that work together to provide logic, memory, and interconnect functions. Most significantly, they did it with standard CMOS manufacturing techniques.

Talking about the impact of the work, Miloš Popovic a co-author on the study from the University of Colorado told HPCwire, “This work is directly aimed at the energy problem in supercomputers.  It will enable reducing the communication energy by about an order of magnitude, and will make communication energy independent of distance of a link — up to 100’s of meters. So, it’s definitely part of the exascale computing story.”

The chip was fabricated using a commercial high-performance 45-nm complementary metal–oxide semiconductor (CMOS) silicon-on-insulator (SOI) process. The authors write: “No changes to the foundry process were necessary to accommodate photonics and all optical devices were designed to comply with the native process-manufacturing rules. This ‘zero-change’ integration enables high-performance transistors on the same chip as optics, reuse of all existing designs in the process, compatibility with electronics design tools, and manufacturing in an existing high-volume foundry.”

On-chip electro-optic transmitters and receivers enable both the microprocessor and the memory to communicate directly to off-chip components using light, without the need for separate chips or components to host the optical devices.

One advantage of light based communication, noted Popović, is that multiple parallel data streams encoded on different colors of light can be sent over one and the same medium – in this case, an optical wire waveguide on a chip, or an off-chip optical fiber of the same kind that as those that form the Internet backbone.

Close-up of light-enabled microprocessor showing optical circuits (left), memory (top) and 2 compute cores (right)
Close-up of light-enabled microprocessor showing optical circuits (left), memory (top) and 2 compute cores (right)

“Another advantage is that the infrared light that we use – and that also TV remotes use – has a physical wavelength shorter than 1 micron, about one hundredth of the thickness of a human hair,” he said. “This enables very dense packing of light communication ports on a chip, enabling huge total bandwidth.” The new chip has a bandwidth density of 300 gigabits per second per square millimeter, about 10 to 50 times greater than packaged electrical-only microprocessors currently on the market.

The big news is the relative ease of manufacture. “This “zero change” approach to integration enables complex electronic-photonic systems on chip to be designed today, in an advanced CMOS foundry. This means high yield, immediate transition to volume production, and the most advanced transistors of any photonic chip (and the largest number of them). These qualities should open up research into systems on chip in many applications including RF signal processing, radar/lidar applications, sensing and imaging, etc.

The authors note, “By showing that a microprocessor with photonic I/O is possible to build today, we’re illustrating the power of this approach.  Incidentally, while we expected photonic devices to not perform as well using this approach as using fabrication customized to photonics, it turns out that in a number of cases they perform better — leveraging the high resolution implant masks, controlled sub-100nm CMOS deep UV lithography, and rich set of material and mask levels available in CMOS.”

As described in the paper, the manufacturing process includes a crystalline-silicon layer that is patterned to form both the body of the electronic transistors and the core of the optical waveguides. A thin buried-oxide layer separates the crystalline-silicon layer from the silicon-handle wafer. Because the buried-oxide layer is <200 nm thick, light propagating in crystalline-silicon waveguides will evanescently leak into the silicon-handle wafer, resulting in high waveguide loss.

To control leakage, selective substrate removal was performed on the chips after electrical packaging to etch away the silicon handle under regions with optical devices. The silicon handle remains intact under the microprocessor and memory (which dissipate the most power) to allow a heat sink to be contacted, if necessary. The researchers report removal of substrate “has a negligible effect on the electronics and the processor is completely functional even with a fully removed substrate.” The full details are best gleaned from the paper itself.

Researchers built the photodetectors of Silicon-Germanium (SiGe), which is present in small amounts in advanced CMOS processing, and selected 1,180nm wavelength for the optical channels as silicon is transparent to that wavelength. No adverse effects were seen and propagation losses were 4.3 dB/cm. The electro-optic transmitter consists of an electro-optic modulator and its electronic driver. The modulator is a silicon micro-ring resonator with a diameter of 10 μm, coupled to a waveguide.

Electrical signals are encoded on light waves in this optical transmitter consisting of a spoked ring modulator, monitoring photodiode (left) and light access port (bottom), all built using the same manufacturing steps and alongside transistor circuits that control them (top)
Electrical signals are encoded on light waves in this optical transmitter consisting of a spoked ring modulator, monitoring photodiode (left) and light access port (bottom), all built using the same manufacturing steps and alongside transistor circuits that control them (top)

It was necessary to create a tuning mechanism report the authors: “As a resonant device, the modulator is highly sensitive to variations in the thickness of the crystalline-silicon layer within and across SOI wafers as well as to spatially and rapidly temporally varying thermal environments created by the electrical components on the chip. Both effects cause λ0 to deviate from the design value, necessitating tuning circuitry. We embedded a 400-Ω resistive microheater inside the ring to efficiently tune λ0 and added a monitoring photodetector weakly coupled to the modulator drop port. When light resonates in the modulator ring, a small fraction of it couples to and illuminates the photodetector.”

Sadasivan Shankar, a longtime senior Intel researcher in semiconductor manufacturing and currently a visiting lecturer in computational science and engineering at Harvard, called the work important. “As mentioned in the paper itself, this is the current strained transistor technology that has been available in the market. [Nevertheless] this is a significant milestone. An optical device for transmission to memory in principle can save energy and also increase the clock cycle,” said Shankar who was not associated with the work.

“The current paradigm in HPC is more moving towards taking computing to data. The integration of optics with electronics on the same chip could enable this without higher energy costs. However, it is not clear that the overall performance is competitive with the state­‐of­‐the-art 14 nm CMOS technology,” said Shankar.

Popovic noted the important next steps for the research include: “1) to demonstrate multi-wavelength (WDM) communication in a processor, and 2) to improve the photonic devices — both of which can be done — to really put to rest questions about the viability of the approach, and 3) to develop new system applications — that will in turn drive us to devise new device concepts within CMOS platforms.”

Challenges aside, the work is a significant step forward. Co-author Chen Sun of UC Berkley said, “At a high-level, our work could solve the interconnect problem of today’s chips inside computers; semiconductor technology has allowed us to do more and more compute on a chip, but has done little to help chips communicate with each other at a higher bandwidth. Furthermore, the amount of power chips spend on communicating with other chips is now >20% of the chip’s power budget.

“With this technology, we could improve chip communication bandwidth by more than an order of magnitude and at lower power. At a lower-level, we have demonstrated an alternative path towards making optical devices on microchips, one that could 100% rely on an existing microchip manufacturing process and be natively integrated with electronics. This is an alternative to how the field of silicon photonics makes devices today, which is typically with the development of a new manufacturing process which no ability to integrate transistors on-chip.”

[i] Single-chip microprocessor that communicates directly using light, Nature

528, 534–538 (24 December 2015) doi:10.1038/nature16454; http://www.nature.com/nature/journal/v528/n7583/full/nature16454.html

Top Photo: Glenn Asakawa
Second Photo: Milos Popovic
Third Photo: Mark Wade

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

Nvidia Leads Alpha MLPerf Benchmarking Round

December 12, 2018

Seven months after the launch of its AI benchmarking suite, the MLPerf consortium is releasing the first round of results based on submissions from Nvidia, Google and Intel. Of the seven benchmarks encompassed in version Read more…

By Tiffany Trader

Neural Network ‘Synapse’ Technology Showcased at IEEE Meeting

December 12, 2018

There’s nice snapshot of advancing work to develop improved neural network “synapse” technologies posted yesterday on IEEE Spectrum. Lower power, ease of use, manufacturability, and performance are all key paramete Read more…

By John Russell

IBM, Nvidia in AI Data Pipeline, Processing, Storage Union

December 11, 2018

IBM and Nvidia today announced a new turnkey AI solution that combines IBM Spectrum Scale scale-out file storage with Nvidia’s GPU-based DGX-1 AI server to provide what the companies call the “the highest performance Read more…

By Doug Black

HPE Extreme Performance Solutions

AI Can Be Scary. But Choosing the Wrong Partners Can Be Mortifying!

As you continue to dive deeper into AI, you will discover it is more than just deep learning. AI is an extremely complex set of machine learning, deep learning, reinforcement, and analytics algorithms with varying compute, storage, memory, and communications needs. Read more…

IBM Accelerated Insights

4 Ways AI Analytics Projects Fail — and How to Succeed

“How do I de-risk my AI-driven analytics projects?” This is a common question for organizations ready to modernize their analytics portfolio. Here are four ways AI analytics projects fail—and how you can ensure success. Read more…

Is Amazon’s Plunge into Server Chips a Watershed Moment?

December 11, 2018

For several years now the big cloud providers – Amazon, Microsoft Azure, Google, et al – have been transforming from technology consumers into technology creators in hardware and software. The most recent example bei Read more…

By John Russell

Nvidia Leads Alpha MLPerf Benchmarking Round

December 12, 2018

Seven months after the launch of its AI benchmarking suite, the MLPerf consortium is releasing the first round of results based on submissions from Nvidia, Goog Read more…

By Tiffany Trader

IBM, Nvidia in AI Data Pipeline, Processing, Storage Union

December 11, 2018

IBM and Nvidia today announced a new turnkey AI solution that combines IBM Spectrum Scale scale-out file storage with Nvidia’s GPU-based DGX-1 AI server to pr Read more…

By Doug Black

Is Amazon’s Plunge into Server Chips a Watershed Moment?

December 11, 2018

For several years now the big cloud providers – Amazon, Microsoft Azure, Google, et al – have been transforming from technology consumers into technology cr Read more…

By John Russell

Mellanox Uses Univa to Extend Silicon Design HPC Operation to Azure

December 11, 2018

Call it a corollary to Murphy’s Law: When a system is most in demand, when end users are most dependent on the system performing as required, when it’s crunch time – that’s when the system is most likely to blow up. Or make you wait in line to use it. Read more…

By Doug Black

Topology Can Help Us Find Patterns in Weather

December 6, 2018

Topology--the study of shapes--seems to be all the rage. You could even say that data has shape, and shape matters. Shapes are comfortable and familiar concepts, so it is intriguing to see that many applications are being recast to use topology. For instance, looking for weather and climate patterns. Read more…

By James Reinders

Zettascale by 2035? China Thinks So

December 6, 2018

Exascale machines (of at least a 1 exaflops peak) are anticipated to arrive by around 2020, a few years behind original predictions; and given extreme-scale performance challenges are not getting any easier, it makes sense that researchers are already looking ahead to the next big 1,000x performance goal post: zettascale computing. Read more…

By Tiffany Trader

Robust Quantum Computers Still a Decade Away, Says Nat’l Academies Report

December 5, 2018

The National Academies of Science, Engineering, and Medicine yesterday released a report – Quantum Computing: Progress and Prospects – whose optimism about Read more…

By John Russell

Revisiting the 2008 Exascale Computing Study at SC18

November 29, 2018

A report published a decade ago conveyed the results of a study aimed at determining if it were possible to achieve 1000X the computational power of the the Read more…

By Scott Gibson

Quantum Computing Will Never Work

November 27, 2018

Amid the gush of money and enthusiastic predictions being thrown at quantum computing comes a proposed cold shower in the form of an essay by physicist Mikhail Read more…

By John Russell

Cray Unveils Shasta, Lands NERSC-9 Contract

October 30, 2018

Cray revealed today the details of its next-gen supercomputing architecture, Shasta, selected to be the next flagship system at NERSC. We've known of the code-name "Shasta" since the Argonne slice of the CORAL project was announced in 2015 and although the details of that plan have changed considerably, Cray didn't slow down its timeline for Shasta. Read more…

By Tiffany Trader

IBM at Hot Chips: What’s Next for Power

August 23, 2018

With processor, memory and networking technologies all racing to fill in for an ailing Moore’s law, the era of the heterogeneous datacenter is well underway, Read more…

By Tiffany Trader

House Passes $1.275B National Quantum Initiative

September 17, 2018

Last Thursday the U.S. House of Representatives passed the National Quantum Initiative Act (NQIA) intended to accelerate quantum computing research and developm Read more…

By John Russell

Summit Supercomputer is Already Making its Mark on Science

September 20, 2018

Summit, now the fastest supercomputer in the world, is quickly making its mark in science – five of the six finalists just announced for the prestigious 2018 Read more…

By John Russell

AMD Sets Up for Epyc Epoch

November 16, 2018

It’s been a good two weeks, AMD’s Gary Silcott and Andy Parma told me on the last day of SC18 in Dallas at the restaurant where we met to discuss their show news and recent successes. Heck, it’s been a good year. Read more…

By Tiffany Trader

US Leads Supercomputing with #1, #2 Systems & Petascale Arm

November 12, 2018

The 31st Supercomputing Conference (SC) - commemorating 30 years since the first Supercomputing in 1988 - kicked off in Dallas yesterday, taking over the Kay Ba Read more…

By Tiffany Trader

CERN Project Sees Orders-of-Magnitude Speedup with AI Approach

August 14, 2018

An award-winning effort at CERN has demonstrated potential to significantly change how the physics based modeling and simulation communities view machine learni Read more…

By Rob Farber

Leading Solution Providers

SC 18 Virtual Booth Video Tour

Advania @ SC18 AMD @ SC18
ASRock Rack @ SC18
DDN Storage @ SC18
HPE @ SC18
IBM @ SC18
Lenovo @ SC18 Mellanox Technologies @ SC18
NVIDIA @ SC18
One Stop Systems @ SC18
Oracle @ SC18 Panasas @ SC18
Supermicro @ SC18 SUSE @ SC18 TYAN @ SC18
Verne Global @ SC18

TACC’s ‘Frontera’ Supercomputer Expands Horizon for Extreme-Scale Science

August 29, 2018

The National Science Foundation and the Texas Advanced Computing Center announced today that a new system, called Frontera, will overtake Stampede 2 as the fast Read more…

By Tiffany Trader

HPE No. 1, IBM Surges, in ‘Bucking Bronco’ High Performance Server Market

September 27, 2018

Riding healthy U.S. and global economies, strong demand for AI-capable hardware and other tailwind trends, the high performance computing server market jumped 28 percent in the second quarter 2018 to $3.7 billion, up from $2.9 billion for the same period last year, according to industry analyst firm Hyperion Research. Read more…

By Doug Black

Nvidia’s Jensen Huang Delivers Vision for the New HPC

November 14, 2018

For nearly two hours on Monday at SC18, Jensen Huang, CEO of Nvidia, presented his expansive view of the future of HPC (and computing in general) as only he can do. Animated. Backstopped by a stream of data charts, product photos, and even a beautiful image of supernovae... Read more…

By John Russell

Germany Celebrates Launch of Two Fastest Supercomputers

September 26, 2018

The new high-performance computer SuperMUC-NG at the Leibniz Supercomputing Center (LRZ) in Garching is the fastest computer in Germany and one of the fastest i Read more…

By Tiffany Trader

Houston to Field Massive, ‘Geophysically Configured’ Cloud Supercomputer

October 11, 2018

Based on some news stories out today, one might get the impression that the next system to crack number one on the Top500 would be an industrial oil and gas mon Read more…

By Tiffany Trader

Intel Confirms 48-Core Cascade Lake-AP for 2019

November 4, 2018

As part of the run-up to SC18, taking place in Dallas next week (Nov. 11-16), Intel is doling out info on its next-gen Cascade Lake family of Xeon processors, specifically the “Advanced Processor” version (Cascade Lake-AP), architected for high-performance computing, artificial intelligence and infrastructure-as-a-service workloads. Read more…

By Tiffany Trader

Google Releases Machine Learning “What-If” Analysis Tool

September 12, 2018

Training machine learning models has long been time-consuming process. Yesterday, Google released a “What-If Tool” for probing how data point changes affect a model’s prediction. The new tool is being launched as a new feature of the open source TensorBoard web application... Read more…

By John Russell

The Convergence of Big Data and Extreme-Scale HPC

August 31, 2018

As we are heading towards extreme-scale HPC coupled with data intensive analytics like machine learning, the necessary integration of big data and HPC is a curr Read more…

By Rob Farber

  • arrow
  • Click Here for More Headlines
  • arrow
Do NOT follow this link or you will be banned from the site!
Share This