Breakthroughs, by their nature, are rarely generated on demand. That said, the energy problem in computing today is so acute that the National Science Foundation and Semiconductor Research Corporation are joining forces to stimulate research into developing ‘breakthroughs’ in energy-efficient computing. The new NSF-NRC grants program, Energy-Efficient Computing: from Devices to Architectures (E2CDA), has a budget of up to $4 million per year and is currently seeking proposals due in late March.

“Truly disruptive breakthroughs are now required, and not just from any one segment of the technology stack. Rather, due to the complexity of the challenges, revolutionary new approaches are needed at each level in the hierarchy. Furthermore, simultaneous co-optimization across all levels is essential for the creation of new, sustainable computing platforms,” is the rather dramatic call in the NSF-SRC solicitation.

The new effort, according to NSF, will specifically support new research to minimize the energy impacts of processing, storing, and moving data within future computing systems, and will be synergistic with other research activities that address other aspects of this overarching energy-constrained computing performance challenge.

“Through this joint solicitation, NSF and SRC aim to support game-changing research that can set the stage for the next paradigm of computing – from mobile devices to data centers – by minimizing the energy impact of future computing systems,” wrote Sankar Basu, one of the E2CDA managers, and NSF program Director for Computing and Communication Foundations, in a blogpost last week.

Clearly the HPC community has been bumping up against power issues for some time and resorted to a wide variety of energy management techniques. (Power dissipation alone has prompted a variety of cooling solutions – but they don’t help other power-related computing challenges.) One near-term power challenge that encompasses the full computing infrastructure is DOE’s stated goal to build an exascale computer that operates with a 25MW budget.

The urgent need now, says NSF-SRC, is research and innovation around devices with switching mechanisms that are fundamentally different from that of the conventional FET (field effect transistor), and architectures than are fundamentally different from the von Neumann architecture.

Shown below is a slide taken from a January webinar on E2CDA and its very familiar contents reflect slide presentations that have taken place throughout the computer industry in recent times. (Here’s a link to the slides from the webinar: https://www.nsf.gov/attachments/137395/public/E2CDA_webinar_slides_2016-01-21.pdf)

The NFS-SRC grants take aim at two broad types (terms of the grant) of approaches to energy reduction and management in computing:

1. Type One. Disruptive system architectures, circuit microarchitectures, and attendant device and interconnect technology aimed at achieving the highest level of computational energy efficiency for general purpose computing systems.

1. Type Two. Revolutionary device concepts and associated circuits and architectures that will greatly extend the practical engineering limits of energy-efficient computation.

NSF-SRC has set ambitious goals. For type one (architecture and connectivity), proposals must target at least a 100X reduction or more in energy per delivered operation as compared to projected high-performance computing (HPC) systems utilizing conventional CMOS architectures and deeply scaled technology at the end of the roadmap. “As just one example of a metric goal, demonstrations that achieve system-level performance of > 1 Giga-MAC/s/nW could be targeted (MAC = multiply and accumulate operations),” spells out the RFP.

Investigation of new alternative connectivity technologies such as plasmonic, photonic, terahertz or “any others that can enable a dramatic lowering of overall system energy dissipation” are encouraged; so are interconnect technologies that enable functionality (such as embedded ‘intelligent’ routing, etc.) beyond point-to-point connectivity and the architectures that implement them are “also within the scope of interest.”

In addition, proposals are strongly encouraged to include an approach for merging heuristic learning and predictive functionality on the same physical platform as a programmable algorithmic capability.

Type two proposals also have a high bar; they must demonstrate new device concepts with the potential to reduce the energy dissipation involved in processing, storing, and moving information by two or more orders of magnitude.

“Any new switch is likely to have characteristics very different from those of a conventional field effect transistor. The interplay between device characteristics and optimum circuit architectures therefore means that circuit architectures must be reconsidered – this includes digital circuits, but also analog, memory, communication, and/or other more specialized functions. Devices combining digital/analog/memory functions may lend themselves particularly well to unconventional information processing architectures,” notes the RFP.

Proposed architectures should enable a broad range of useful functions, rather than being dedicated to one function or a few particular functions. More details for the terms of the E2CDA grants are show here (below).

Deadline for proposals is March 28. The E2CDA solicitation was posted on NSF on December 29, 2015, with a webinar held on January 21. No awards have been made as of this writing. That Basu wrote the guest post on the The CCC Blog (Computing Community Consortium) last week possibly suggests that responses to the solicitation may have been low so far.

The solicitation also offers guidance on what not to propose. Here are a few examples for both types:

Type one (proposals not sought):

• Evolutionary extensions of existing general purpose computing platform architectures.
• Systems that preclude substantially expanding the functionality and performance capabilities of general purpose computing, even if they are also aimed at significantly improving the overall level of energy efficiency.
• System architectures that cannot be demonstrated to economically support the levels of reliability and physical dimension requirements projected for the future applications being targeted.
  System architectures that are not sufficiently scalable to support a broad base of applications.

Type two (proposals not sought):

• Materials or device concepts that incrementally extend the capabilities of commercially established devices for logic and memory.
• CMOS-based approaches to energy-conserving circuits and architectures;
• Device concepts already the focus of research within established projects and centers, unless the proposed research is a substantive step beyond the currently-funded research.
• Highly-specialized circuit architectures (“accelerators”) suited to a particular function or a limited set of functions, unless these circuits can be envisioned as economically integrated in a hybrid system capable of more generalized functions.
• Devices and architectures for quantum computing – although proposals that explore the semi-classical regime (perhaps instantiating state variables with small ensembles of quantum states) or proposals that embrace some attributes of quantum computing achievable in the classical limit (such as energy-conserving circuits) are welcome.

Here is a link for information on the E2CDA grants: http://www.nsf.gov/pubs/2016/nsf16526/nsf16526.htm