NVIDIA Unleashes Monster Pascal GPU Card at GTC16

By Tiffany Trader

April 5, 2016

Earlier today (Tuesday) at the seventh-annual GPU Technology Conference (GTC) in San Jose, Calif., NVIDIA revealed its first Pascal-architecture based GPU card, the P100, calling it “the most advanced accelerator ever built.” The P100 is based on the NVIDIA Pascal GP100 GPU — a successor to the Kepler GK110/210 — and is aimed squarely at HPC, technical computing and deep learning workloads.

Packing a whopping 5.3 teraflops of double-precision floating point performance, the P100 is NVIDIA’s most performant chip to date. And with 15.3 billion transistors, it’s also the largest GPU that NVIDIA has ever made in spite of it being built on TSMC’s 16nm FinFET manufacturing process.

The P100 is the flagship Pascal architecture offering, and it’s also the first product to implement the heralded HBM2 and NVLink technologies. During his keynote address, NVIDIA CEO Jen-Hsun Huang said the chip had entered volume production and would ship by first quarter 2017. Partners Dell, HPE, Cray and IBM are expected to come out with Pascal-equipped servers by the end of 2016, with production availability in early 2017.

Huang also showed how the new Pascal GPU fits in with the Tesla family. The new DGX-1 deep learning supercomputer is shown all the way to the right. With a price tag of $129,000 the DGX-1 puts the equivalent of 250 servers in a box, said Huang. It packs eight of the new P100 GPUs and 7 TB of SSD storage and can pump out up to 170 teraflops of half-precision floating point performance.

GTC16 Tesla Family full 1400x

In a separate presentation, Lars Nyland, NVIDIA senior architect, and Mark Harris, chief technologist of GPU computing software at NVIDIA, provided a deep dive into the new architecture. Before unpacking the new features and specs, the duo looked at some real-world performance speedups for the P100. This chart depicts the benefits of the faster GPU and the high-bandwidth NVLink interconnect technology.

NVIDIA Tesla P100 chart

GPU Breakdown

The cradle for computation in Tesla GPUs is the SM, the streaming multiprocessor. The SM creates, manages, schedules and executes instructions from many threads in parallel. The Tesla GP100 GPU has 60 SMs. For the P100, NVIDIA has enabled 56 of them for a total of 3,584 CUDA (enabled) cores. Memory bandwidth is 720 GB/s and the memory size is 16 GB.

There are 64 CUDA cores in the GP100 SM, which at first seems small in comparison to Maxwell’s SM with 128, but there is a reason. To arrive at the GP100 SM, NVIDIA started with a Maxwell SM and chopped it in half.

“The cores are your most important resource on the SM and if you don’t use them in any particular clock cycle, you are wasting your chip,” explained Nyland. “What we wanted to do was improve the efficiency to make them be used more often. We started with the Maxwell SM and we cut it in half – that gives us two P100 SMs. We could have stopped here, but we added the 64-bit floating point double precision cores and then we doubled the occupancy, we doubled the number of warps per P100 SM so that the occupancy went back to being equivalent to Maxwell SM. Then we also doubled the register files and finally we duplicated the shared memory – so now we have two SMs with 64 cores each from what we started with, one Maxwell 128 core SM.”

Pascal GP100_SM_diagramThe net effect, the NVIDIA reps go on to explain, is that the GP100 SM has more resources per core. It has twice the number of registers more core, 1.33x more shared memory capacity, 2x shared memory bandwidth and twice as many warps resident at the same time on the SMs.

The overall impact is higher instruction throughput leading to higher utilization when running codes. “There’s a big effort that’s gone into making sure you get more value out of every core,” said Harris.

“We’ve put more resources around each core” Nyland added, “By having more warps ready, the scheduler has more to choose from and so it has more opportunities to run something than it would if there were fewer warps. By having more register, we can have higher occupancy. And then having a shared memory, we have double the bandwidth and less contention, less cores shared with the shared memory so there is more access. All of this adds up to more utilization of the cores, which is the real goal.”

Floating point is cited as another critical resource. The three sizes – half-precision, single-precision and double-precision — all fit the IEEE standard. The peak speed of 5.2 teraflops double-precision performance doubles to 10.6 teraflops running in single-precision floating point mode. Double it again, and you get 21 peak teraflops of half-precision floating point performance — another first.

“GPUs have used half-precision for at least a dozen years as a storage mechanism to save space — for textures — but we’ve never built an arithmetic pipeline to implement the 16-bit floating point directly, we’ve always converted it,” Nyland said. “What we’ve done is left it in its native size and then pair it together and execute an instruction on a pair of values every clock – this is compared to the single-precision where we execute one instruction every clock and the double-precision runs at one every two clocks.”

NVIDIA has also added atomic addition for 64-bit floating point values.

GTC16 Pascal Tesla P100 comparison 700x

NVLink

One of the most important new features that debuted with the Pascal architecture is NVLink, NVIDIA’s communications protocol that allows high-speed communication from one GPU to another and to future NVLink-enabled CPUs as well. The point-to-point interconnect is said to allow data sharing at rates five to 12 times faster than traditional PCI Express Gen 3 (PCIe). And its compatibility with the GPU ISA means it can support shared memory multiprocessing workloads.

Currently implemented in Tesla P100 accelerator boards and Pascal GP100 GPUs, NVLink supports reads, writes and atomics between GPUs. There are four NVLinks on every P100 GPU. A single link supports up to 40 GB/sec of bidirectional bandwidth between the endpoints and links can be connected in a gang to enable an aggregate maximum theoretical bandwidth of 160 GB/sec bidirectional bandwidth per P100. The ability to have four or eight GPUs all sharing data with each other is the real benefit of NVlink, said Harris. “We can build really powerful machines and still program them with familiar programming models,” he added.

NVIDIA NVLink 8-GPU-hybrid-cube-mesh 800x

NVLink can also be coupled with an NVLink enabled CPU, like the future POWER CPU that IBM has announced. In this configuration, four P100 GPUs can be fully connected in a gang and they’ll have a link that connects to the CPU. The GPUs will thus be able to access all the memory of the other GPUs and CPU memory.

High Bandwidth Memory 2

The other major first for P100 is its use of HBM2 stacked memory. This technology enables multiple layers of DRAM components to be integrated vertically on the package along with the GPU. The P100 accelerators have four 4-die HBM2 stacks, for a total of 16 GB of memory, and 720 GB/s peak bandwidth.

With HBM2, error correcting code (ECC) functionality is free, the NVIDIA reps noted. What this means is there is no capacity taken away and there’s no processing performance penalty associated with using ECC. This wasn’t the case with the GDDR memories. For those, NVIDIA implemented an ECC scheme that used some of the memory for the ECC bit data and they had to create that data themselves, which had a slight penalty.

Unified Memory

Pascal has also expanded on the unified memory features of CUDA 6 by adding support for large address spaces and page faulting capability. Because Kepler and Maxwell weren’t allowed to page fault, the developer was only allowed to allocate unified memory up to the size of the GPU’s physical memory. Also, because the GPU can page fault, when you launch a kernel, any pages that were migrated to the CPU need to be migrated back to the GPU before the kernel can run – this translates to launch overhead. This meant that on Kepler and Maxwell the CPU and GPU code could not simultaneously access the same memory allocations.

“With the page migration engine, the larger address space and the ability to page fault, you now get all of these things you couldn’t do before,” explained Nyland. “You can allocate beyond the size of the GPU memory up to the physical system memory size, which means you can oversubscribe the GPU memory and do the processing of large scale models out of core. You can now simultaneously access those allocations from the CPU and GPU without fatal errors. This means you have much finer-grained communication between the processors but you do still have to take care of proper synchronization so you don’t have race conditions. You can even do unified memory atomic operations, and across NVLink these are native.”

In the future, on systems that support it, Pascal enables the possibility of using the system allocator to allocate unified memory. In this case, malloc would be able to pass those pointers to CPU or GPU and share that data. NVIDIA is working with Red Hat and the Linux community on the operating system changes that are necessary to unlock this functionality, reported Nyland.

More to come…

This was the first major walk-through of the Pascal architecture and GPU launch, however that’s by no means all of it. NVIDIA will be discussing other GP100 features — such as preemption and a larger L2 cache — in the days and weeks to come. A white paper is said to be forthcoming and we will link to it here when it’s available. For now, if you are hungry for more Pascal information, check out this blog post by Mark Harris, which reprises the content of today’s deep dive session.

Pricing for the Tesla P100 is not yet available and shipping is still about a year away, but there is a way to get your hands on one. The GPUs are available for $16,125 each in quantities of eight — if you spring for the DGX-1. NVIDIA also makes select hardware available to its joint lab partners and its early access program partners.

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

Women Coders from Russia, Italy, and Poland Top Study

January 17, 2017

According to a study posted on HackerRank today the best women coders as judged by performance on HackerRank challenges come from Russia, Italy, and Poland. Read more…

By John Russell

Spurred by Global Ambitions, Inspur in Joint HPC Deal with DDN

January 17, 2017

Inspur, the fast-growth cloud computing and server vendor from China that has several systems on the current Top500 list, and DDN, a leader in high-end storage, have announced a joint sales and marketing agreement to produce solutions based on DDN storage platforms integrated with servers, networking, software and services from Inspur. Read more…

By Doug Black

Weekly Twitter Roundup (Jan. 12, 2017)

January 12, 2017

Here at HPCwire, we aim to keep the HPC community apprised of the most relevant and interesting news items that get tweeted throughout the week. Read more…

By Thomas Ayres

NSF Seeks Input on Cyberinfrastructure Advances Needed

January 12, 2017

In cased you missed it, the National Science Foundation posted a “Dear Colleague Letter” (DCL) late last week seeking input on needs for the next generation of cyberinfrastructure to support science and engineering. Read more…

By John Russell

HPE Extreme Performance Solutions

Remote Visualization: An Integral Technology for Upstream Oil & Gas

As the exploration and production (E&P) of natural resources evolves into an even more complex and vital task, visualization technology has become integral for the upstream oil and gas industry. Read more…

NSF Approves Bridges Phase 2 Upgrade for Broader Research Use

January 12, 2017

The recently completed phase 2 upgrade of the Bridges supercomputer at the Pittsburgh Supercomputing Center (PSC) has been approved by the National Science Foundation (NSF) making it now available for research allocations to the national scientific community, according to an announcement posted this week on the XSEDE web site. Read more…

By John Russell

Clemson Software Optimizes Big Data Transfers

January 11, 2017

Data-intensive science is not a new phenomenon as the high-energy physics and astrophysics communities can certainly attest, but today more and more scientists are facing steep data and throughput challenges fueled by soaring data volumes and the demands of global-scale collaboration. Read more…

By Tiffany Trader

For IBM/OpenPOWER: Success in 2017 = (Volume) Sales

January 11, 2017

To a large degree IBM and the OpenPOWER Foundation have done what they said they would – assembling a substantial and growing ecosystem and bringing Power-based products to market, all in about three years. Read more…

By John Russell

UberCloud Cites Progress in HPC Cloud Computing

January 10, 2017

200 HPC cloud experiments, 80 case studies, and a ton of hands-on experience gained, that’s the harvest of four years of UberCloud HPC Experiments. Read more…

By Wolfgang Gentzsch and Burak Yenier

Spurred by Global Ambitions, Inspur in Joint HPC Deal with DDN

January 17, 2017

Inspur, the fast-growth cloud computing and server vendor from China that has several systems on the current Top500 list, and DDN, a leader in high-end storage, have announced a joint sales and marketing agreement to produce solutions based on DDN storage platforms integrated with servers, networking, software and services from Inspur. Read more…

By Doug Black

For IBM/OpenPOWER: Success in 2017 = (Volume) Sales

January 11, 2017

To a large degree IBM and the OpenPOWER Foundation have done what they said they would – assembling a substantial and growing ecosystem and bringing Power-based products to market, all in about three years. Read more…

By John Russell

UberCloud Cites Progress in HPC Cloud Computing

January 10, 2017

200 HPC cloud experiments, 80 case studies, and a ton of hands-on experience gained, that’s the harvest of four years of UberCloud HPC Experiments. Read more…

By Wolfgang Gentzsch and Burak Yenier

A Conversation with Women in HPC Director Toni Collis

January 6, 2017

In this SC16 video interview, HPCwire Managing Editor Tiffany Trader sits down with Toni Collis, the director and founder of the Women in HPC (WHPC) network, to discuss the strides made since the organization’s debut in 2014. Read more…

By Tiffany Trader

BioTeam’s Berman Charts 2017 HPC Trends in Life Sciences

January 4, 2017

Twenty years ago high performance computing was nearly absent from life sciences. Today it’s used throughout life sciences and biomedical research. Genomics and the data deluge from modern lab instruments are the main drivers, but so is the longer-term desire to perform predictive simulation in support of Precision Medicine (PM). There’s even a specialized life sciences supercomputer, ‘Anton’ from D.E. Shaw Research, and the Pittsburgh Supercomputing Center is standing up its second Anton 2 and actively soliciting project proposals. There’s a lot going on. Read more…

By John Russell

Fast Rewind: 2016 Was a Wild Ride for HPC

December 23, 2016

Some years quietly sneak by – 2016 not so much. It’s safe to say there are always forces reshaping the HPC landscape but this year’s bunch seemed like a noisy lot. Among the noisemakers: TaihuLight, DGX-1/Pascal, Dell EMC & HPE-SGI et al., KNL to market, OPA-IB chest thumping, Fujitsu-ARM, new U.S. President-elect, BREXIT, JR’s Intel Exit, Exascale (whatever that means now), NCSA@30, whither NSCI, Deep Learning mania, HPC identity crisis…You get the picture. Read more…

By John Russell

AWI Uses New Cray Cluster for Earth Sciences and Bioinformatics

December 22, 2016

The Alfred Wegener Institute, Helmholtz Centre for Polar and Marine Research (AWI), headquartered in Bremerhaven, Germany, is one of the country's premier research institutes within the Helmholtz Association of German Research Centres, and is an internationally respected center of expertise for polar and marine research. In November 2015, AWI awarded Cray a contract to install a cluster supercomputer that would help the institute accelerate time to discovery. Now the effort is starting to pay off. Read more…

By Linda Barney

Addison Snell: The ‘Wild West’ of HPC Disaggregation

December 16, 2016

We caught up with Addison Snell, CEO of HPC industry watcher Intersect360, at SC16 last month, and Snell had his expected, extensive list of insights into trends driving advanced-scale technology in both the commercial and research sectors. Read more…

By Doug Black

AWS Beats Azure to K80 General Availability

September 30, 2016

Amazon Web Services has seeded its cloud with Nvidia Tesla K80 GPUs to meet the growing demand for accelerated computing across an increasingly-diverse range of workloads. The P2 instance family is a welcome addition for compute- and data-focused users who were growing frustrated with the performance limitations of Amazon's G2 instances, which are backed by three-year-old Nvidia GRID K520 graphics cards. Read more…

By Tiffany Trader

US, China Vie for Supercomputing Supremacy

November 14, 2016

The 48th edition of the TOP500 list is fresh off the presses and while there is no new number one system, as previously teased by China, there are a number of notable entrants from the US and around the world and significant trends to report on. Read more…

By Tiffany Trader

Vectors: How the Old Became New Again in Supercomputing

September 26, 2016

Vector instructions, once a powerful performance innovation of supercomputing in the 1970s and 1980s became an obsolete technology in the 1990s. But like the mythical phoenix bird, vector instructions have arisen from the ashes. Here is the history of a technology that went from new to old then back to new. Read more…

By Lynd Stringer

For IBM/OpenPOWER: Success in 2017 = (Volume) Sales

January 11, 2017

To a large degree IBM and the OpenPOWER Foundation have done what they said they would – assembling a substantial and growing ecosystem and bringing Power-based products to market, all in about three years. Read more…

By John Russell

Container App ‘Singularity’ Eases Scientific Computing

October 20, 2016

HPC container platform Singularity is just six months out from its 1.0 release but already is making inroads across the HPC research landscape. It's in use at Lawrence Berkeley National Laboratory (LBNL), where Singularity founder Gregory Kurtzer has worked in the High Performance Computing Services (HPCS) group for 16 years. Read more…

By Tiffany Trader

Dell EMC Engineers Strategy to Democratize HPC

September 29, 2016

The freshly minted Dell EMC division of Dell Technologies is on a mission to take HPC mainstream with a strategy that hinges on engineered solutions, beginning with a focus on three industry verticals: manufacturing, research and life sciences. "Unlike traditional HPC where everybody bought parts, assembled parts and ran the workloads and did iterative engineering, we want folks to focus on time to innovation and let us worry about the infrastructure," said Jim Ganthier, senior vice president, validated solutions organization at Dell EMC Converged Platforms Solution Division. Read more…

By Tiffany Trader

Lighting up Aurora: Behind the Scenes at the Creation of the DOE’s Upcoming 200 Petaflops Supercomputer

December 1, 2016

In April 2015, U.S. Department of Energy Undersecretary Franklin Orr announced that Intel would be the prime contractor for Aurora: Read more…

By Jan Rowell

Enlisting Deep Learning in the War on Cancer

December 7, 2016

Sometime in Q2 2017 the first ‘results’ of the Joint Design of Advanced Computing Solutions for Cancer (JDACS4C) will become publicly available according to Rick Stevens. He leads one of three JDACS4C pilot projects pressing deep learning (DL) into service in the War on Cancer. Read more…

By John Russell

Leading Solution Providers

D-Wave SC16 Update: What’s Bo Ewald Saying These Days

November 18, 2016

Tucked in a back section of the SC16 exhibit hall, quantum computing pioneer D-Wave has been talking up its new 2000-qubit processor announced in September. Forget for a moment the criticism sometimes aimed at D-Wave. This small Canadian company has sold several machines including, for example, ones to Lockheed and NASA, and has worked with Google on mapping machine learning problems to quantum computing. In July Los Alamos National Laboratory took possession of a 1000-quibit D-Wave 2X system that LANL ordered a year ago around the time of SC15. Read more…

By John Russell

CPU Benchmarking: Haswell Versus POWER8

June 2, 2015

With OpenPOWER activity ramping up and IBM’s prominent role in the upcoming DOE machines Summit and Sierra, it’s a good time to look at how the IBM POWER CPU stacks up against the x86 Xeon Haswell CPU from Intel. Read more…

By Tiffany Trader

Nvidia Sees Bright Future for AI Supercomputing

November 23, 2016

Graphics chipmaker Nvidia made a strong showing at SC16 in Salt Lake City last week. Read more…

By Tiffany Trader

New Genomics Pipeline Combines AWS, Local HPC, and Supercomputing

September 22, 2016

Declining DNA sequencing costs and the rush to do whole genome sequencing (WGS) of large cohort populations – think 5000 subjects now, but many more thousands soon – presents a formidable computational challenge to researchers attempting to make sense of large cohort datasets. Read more…

By John Russell

Beyond von Neumann, Neuromorphic Computing Steadily Advances

March 21, 2016

Neuromorphic computing – brain inspired computing – has long been a tantalizing goal. The human brain does with around 20 watts what supercomputers do with megawatts. And power consumption isn’t the only difference. Fundamentally, brains ‘think differently’ than the von Neumann architecture-based computers. While neuromorphic computing progress has been intriguing, it has still not proven very practical. Read more…

By John Russell

The Exascale Computing Project Awards $39.8M to 22 Projects

September 7, 2016

The Department of Energy’s Exascale Computing Project (ECP) hit an important milestone today with the announcement of its first round of funding, moving the nation closer to its goal of reaching capable exascale computing by 2023. Read more…

By Tiffany Trader

Dell Knights Landing Machine Sets New STAC Records

November 2, 2016

The Securities Technology Analysis Center, commonly known as STAC, has released a new report characterizing the performance of the Knight Landing-based Dell PowerEdge C6320p server on the STAC-A2 benchmarking suite, widely used by the financial services industry to test and evaluate computing platforms. The Dell machine has set new records for both the baseline Greeks benchmark and the large Greeks benchmark. Read more…

By Tiffany Trader

What Knights Landing Is Not

June 18, 2016

As we get ready to launch the newest member of the Intel Xeon Phi family, code named Knights Landing, it is natural that there be some questions and potentially some confusion. Read more…

By James Reinders, Intel

  • arrow
  • Click Here for More Headlines
  • arrow
Share This