Intel’s Omni-Path Architecture (OPA), a centerpiece of its Scalable System Framework (SSF), has been shipping for a full quarter now and according to Barry Davis, general manager, HPC Compute & Networks at Intel, OPA is doing well contrary to suggestions from a competitor. The two main contestants, of course, are Intel and Mellanox and the battle between Intel’s OPA and Mellanox’s Enhanced Data Rate (EDR) InfiniBand is just heating up.
Leaving technical merits aside for a moment – Mellanox recently contributed a commentary to HPCwire (The Ultimate Debate – Interconnect Offloading Versus Onloading) advocating the superiority of its offloading approach – Intel OPA seems to be gaining steady traction in the early stages of its rollout. Among the more notable public wins are contracts with National Nuclear Security Administration’s Tri Labs (Capacity Technology Systems (CTS-1) program), Texas Advanced Computing Center, the University of Cambridge, the Alfred Wegener Institute, and the Pittsburgh Supercomputing Center.
The NNSA win, said Davis, involved head-to-head interconnect competition with OPA winning out. The CTS-1 award, won with Penguin Computing (servers and systems integration), is for $39 million and will provide, “35,000 nodes spread over the next three years. We’ll be delivering approximately 20,000 nodes this year of which about two thirds have been delivered,” he said.
Matt Leininger, deputy for advanced technology projects at LLNL and acquisition manager of systems under the CTS program is quoted in a recent Davis blog (The Data Stack) saying the selection of OPA “was based on our performance benchmarking and assessment of any technical and schedule risks. Our expectation is that Intel OPA will continue to provide improved scalability in the new clusters.”
Clearly it’s early days for both OPA and EDR and competitive zeal is running high. Davis said that OPA has already racked up dozens of wins, including big ones in all the major geographies.
Just last week, said Davis, Intel won the largest award in Japan so far this year though he did not identify the customer. Cost-performance was the deciding factor, according to Davis, who said selecting OPA would allow the client to afford almost two additional petaflops of performance. “This will allow them to run more applications simultaneously, and provide better time to solution for those applications, as well as a higher listing on the top 500,” contends Davis.
Intel has bet big on OPA as part of its SSF vision moving forward. One of the clearer distinctions between the OPA and EDR offerings is the use of offloading and onloading approaches to handling network traffic. In brief:
- Offloading, used by Mellanox, moves much of the network communications processing off the host CPU and onto network devices. The straightforward idea is to free up host CPU cycles for application execution.
- Onloading, emphasized by Intel, relies on the host CPU to process communications traffic. As the communication processing burden grows – for example as the number of cores and nodes grow – more host cycles can be required for traffic communications and latency can be increased.
The devil is in the details. Indeed, Intel agrees offloading is sometimes a good idea, but argues strongly that OPA is not just an onloading architecture. Far from it, Intel describes OPA as a hybrid architecture that chooses off- or onloading processing depending upon and the size and type of data as well as user-configurations.
“Compute data coming out of MPI tends to be very high message rate, relatively small size for each message, and highly latency sensitive. There we do use an onload method because we found it to be the best way to move data,” said Joe Yaworski, director of marketing, HPC Networking at Intel. “We keep in memory all of the addressing information for every node, core, and process running that requires this communications.”
The result said, Yaworski, is a very consistent latency from a small number of nodes up to a very large number of nodes independent of the cores, and that includes “very consistent latency whether it’s well-formed communications or random in nature.”
OPA can also perform offloads said Yaworski, “So we do direct application to application writes without impacting the processor. For things like moving lots of data that would be typically found in a file system such as Lustre, [where] the typical size of moving data is a megabyte; we do a direct write from the application through to the other adapter which places it directly in the application’s memory without ever interrupting the processor,” Yaworski said.
The point, insist Davis and Yaworski, is that OPA can do both automatically. “A user can change those automatic settings to get good movement of data based on its characteristics whether it’s highly latency sensitive, small message sizes, such as you’d find in compute or large blocks of data where you want to move it and place it directly into the application user space like a files systems,” he said adding OPA supports full RDMA where it makes sense to use RDMA.
Apart from the generic onload versus offload argument (missed cache hits can bog down offloading; increased host CPU cycles can slow onloading) Intel argues that its use of a different communications library – PSM or performance scaled messaging – is instrumental in minimizing CPU cycles spent on communications in the onloading approach. “PSM when you compare it to [InfiniBand] verbs for doing a small MPI messages, it requires 1/10th of the instructions to complete a communications and the reason is that we designed PSM to be perfectly matched to the semantics of MPI. It’s very efficient communications layer.”