IBM Puts 3D XPoint on Notice with 3 Bits/Cell PCM Breakthrough

By Tiffany Trader

May 18, 2016

IBM scientists have broken new ground in the development of a phase change memory technology (PCM) that puts a target on competing 3D XPoint technology from Intel and Micron. IBM successfully stored 3 bits per cell in a 64k-cell array that had been pre-cycled 1 million times and exposed to temperatures up to 75∘C. A paper describing the advance was presented this week at the IEEE International Memory Workshop in Paris.

Phase-change memory is an up-and-coming non-volatile memory technology — a storage-class memory that bridges the divide between expensive performant, volatile memory (namely DRAM), and slower persistent storage (flash or hard disk drives). According to IBM, having the ability to reliably fit 3 bits per cell is what will make this technology price-competitive with flash.

With memory demands riding the tide of big data, phase change memory has a lot to recommend it but to be a market success, the economics must work, say the authors, and being able to store multiple bits per memory cell is essential for keeping costs under control.

Using a combination of electrical sensing techniques and signal processing technologies, the researchers have shown for the first time the the viability of Triple-Level-Cell (TLC) storage in phase-change memory cells. The researchers addressed challenges related to multi-bit PCM including drift, variability, temperature sensitivity and endurance cycling with two innovative enabling technologies:

(a) an advanced, nonresistance cell-state metric that exhibits robustness to drift and PCM noise, and (b) an adaptive level-detection and modulation-coding framework that enables further resilience to drift, noise and temperature variation effects.

Dr. Haris Pozidis

At the Paris IEEE event, Dr. Haris Pozidis, an author of the paper and the manager of non-volatile memory research at IBM Research – Zurich, explained that phase change memory is based on the properties that a chalcogenide alloy has when heat is applied. A laser pulse is used to switch the ally between its polycrystalline and amorphous (glassy) state. By controlling heating and cooling, one can switch reliably between these two phases, said Pozidis. The principle of storing more bits per cell is based on the fact that the alloy can also exist in an intermediate phase, which is a mixture of a crystalline and amorphous state that gives rise to an intermediate resistance.

“In terms of basic characteristics,” said Pozidis, “phase change memory exhibits latency on the order of hundred nanoseconds to a couple microseconds, compared to hundreds of microseconds to milliseconds for flash, so about three orders of magnitude faster. In terms of write endurance, we have demonstrated one million cycles, but there are other demonstrations that have shown in excess of one million cycles and therefore this brings it to at least 1000x or even more than flash. In terms of cost, this is a crucial attribute, because this is what will pave the way for PCM acceptance in the marketplace, and there PCM is believed to be between DRAM and flash. With this technology of storing 3 bits per cell, we believe that the cost per bit of PCM will potentially approach that of flash today.”

The TLC PCM offers a moderate data retention of 10 days at temperatures as high as 75∘C. Beyond being persistent, IBM’s PCM technology is radiation-hardened and it offers through random access capability and write in place capability unlike flash. It’s also very scalable, noted Pozidis, with research showing PCM properties on materials down to less than 10nm in diameter.

IBM has plans to integrate PCM at a cluster and datacenter level using low-latency networking and support from system software to enable new use cases for data-intensive applications. Strides were made toward this goal at the 2016 OpenPower summit, when IBM scientists demonstrated the attachment of its second-generation phase-change memory to POWER8-based servers via the CAPI protocol. Latency was observed for 128-byte read/write access from/to PCM DIMMs on a POWER8 server. 99 percent of reads completed within 3.9 us.

“Right now it’s a technology that has just seen the light of day in the form of a controlled release,” said IDC analyst Ashish Nadkarni, who was pre-briefed on the announcement, “so it’s going to take some time before it reaches the point [of flash cost parity]. Right now it’s between DRAM and NAND, and it’s more a period of time where it’s inched closer toward the cost of NAND, but as the cost of NAND itself goes down, PCM today is somewhere in the middle and it has to move faster to catch up. I suspect it will take a couple years before it’s comparable. They still need to find suppliers who can manufacture the technology; they need to be able to iron out all the kinks, and the supply chain has to fall in line.”

The IBM effort is competing with 3D XPoint, the non-volatile memory play from Intel and Micron that was announced last summer. Those partners have been less forthcoming with the specifics of the enabling technology, which is speculated to be either ReRAM- or PCM-based, but like IBM’s PCM device, 3D XPoint targets that gap between speedy RAM and high-capacity, low-cost flash. IBM hasn’t publicly announced a partner yet, but it has worked with SK Hynix in the past.

“Clearly there’s going to be a competitive landscape,” Nadkarni reflected. “Samsung might enter the game as well. Intel and Micron have the benefit of being the first born, but they haven’t started shipping yet. For IBM, the benefit they have is they can start deploying it in their own products. Intel and Micron have to find other suppliers who can use the technology in their products. It’s not clear who’s superior today but from IBM’s perspective being able to stuff 3 bits in a single cell is a big deal as is being able to control the state of the bits based on temperature.”

The experiments were carried out on a prototype PCM chip consisting of a 2 × 2 Mcell array of 4 Mcells with a 4-bank interleaving architecture, connected to a standard integrated circuit board. The memory array size is 2 × 1000 μm × 800 μm. The prototype chip uses 90nm CMOS baseline technology.

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

Quantum Rolls – DOE Dishes $218M; NSF Awards $31M; US Releases ‘Strategic Overview’

September 24, 2018

It was quite a day for U.S. quantum computing. In conjunction with the White House Summit on Advancing American Leadership in Quantum Information Science (QIS) held today, the Department of Energy announced $218 million Read more…

By John Russell

Russian and American Scientists Achieve 50% Increase in Data Transmission Speed

September 20, 2018

As high-performance computing becomes increasingly data-intensive and the demand for shorter turnaround times grows, data transfer speed becomes an ever more important bottleneck. Now, in an article published in IEEE Tra Read more…

By Oliver Peckham

IBM to Brand Rescale’s HPC-in-Cloud Platform

September 20, 2018

HPC (or big compute)-in-the-cloud platform provider Rescale has formalized the work it’s been doing in partnership with public cloud vendors by announcing its Powered by Rescale program – with IBM as its first named Read more…

By Doug Black

HPE Extreme Performance Solutions

Introducing the First Integrated System Management Software for HPC Clusters from HPE

How do you manage your complex, growing cluster environments? Answer that big challenge with the new HPC cluster management solution: HPE Performance Cluster Manager. Read more…

IBM Accelerated Insights

Clouds Over the Ocean – a Healthcare Perspective

Advances in precision medicine, genomics, and imaging; the widespread adoption of electronic health records; and the proliferation of medical Internet of Things (IoT) and mobile devices are resulting in an explosion of structured and unstructured healthcare-related data. Read more…

Democratization of HPC Part 1: Simulation Sheds Light on Building Dispute

September 20, 2018

This is the first of three articles demonstrating the growing acceptance of High Performance Computing especially in new user communities and application areas. Major reasons for this trend are the ongoing improvements i Read more…

By Wolfgang Gentzsch

Quantum Rolls – DOE Dishes $218M; NSF Awards $31M; US Releases ‘Strategic Overview’

September 24, 2018

It was quite a day for U.S. quantum computing. In conjunction with the White House Summit on Advancing American Leadership in Quantum Information Science (QIS) Read more…

By John Russell

Summit Supercomputer is Already Making its Mark on Science

September 20, 2018

Summit, now the fastest supercomputer in the world, is quickly making its mark in science – five of the six finalists just announced for the prestigious 2018 Read more…

By John Russell

House Passes $1.275B National Quantum Initiative

September 17, 2018

Last Thursday the U.S. House of Representatives passed the National Quantum Initiative Act (NQIA) intended to accelerate quantum computing research and developm Read more…

By John Russell

Nvidia Accelerates AI Inference in the Datacenter with T4 GPU

September 14, 2018

Nvidia is upping its game for AI inference in the datacenter with a new platform consisting of an inference accelerator chip--the new Turing-based Tesla T4 GPU- Read more…

By George Leopold

DeepSense Combines HPC and AI to Bolster Canada’s Ocean Economy

September 13, 2018

We often hear scientists say that we know less than 10 percent of the life of the oceans. This week, IBM and a group of Canadian industry and government partner Read more…

By Tiffany Trader

Rigetti (and Others) Pursuit of Quantum Advantage

September 11, 2018

Remember ‘quantum supremacy’, the much-touted but little-loved idea that the age of quantum computing would be signaled when quantum computers could tackle Read more…

By John Russell

How FPGAs Accelerate Financial Services Workloads

September 11, 2018

While FSI companies are unlikely, for competitive reasons, to disclose their FPGA strategies, James Reinders offers insights into the case for FPGAs as accelerators for FSI by discussing performance, power, size, latency, jitter and inline processing. Read more…

By James Reinders

Update from Gregory Kurtzer on Singularity’s Push into FS and the Enterprise

September 11, 2018

Container technology is hardly new but it has undergone rapid evolution in the HPC space in recent years to accommodate traditional science workloads and HPC systems requirements. While Docker containers continue to dominate in the enterprise, other variants are becoming important and one alternative with distinctly HPC roots – Singularity – is making an enterprise push targeting advanced scale workload inclusive of HPC. Read more…

By John Russell

TACC Wins Next NSF-funded Major Supercomputer

July 30, 2018

The Texas Advanced Computing Center (TACC) has won the next NSF-funded big supercomputer beating out rivals including the National Center for Supercomputing Ap Read more…

By John Russell

IBM at Hot Chips: What’s Next for Power

August 23, 2018

With processor, memory and networking technologies all racing to fill in for an ailing Moore’s law, the era of the heterogeneous datacenter is well underway, Read more…

By Tiffany Trader

Requiem for a Phi: Knights Landing Discontinued

July 25, 2018

On Monday, Intel made public its end of life strategy for the Knights Landing "KNL" Phi product set. The announcement makes official what has already been wide Read more…

By Tiffany Trader

CERN Project Sees Orders-of-Magnitude Speedup with AI Approach

August 14, 2018

An award-winning effort at CERN has demonstrated potential to significantly change how the physics based modeling and simulation communities view machine learni Read more…

By Rob Farber

ORNL Summit Supercomputer Is Officially Here

June 8, 2018

Oak Ridge National Laboratory (ORNL) together with IBM and Nvidia celebrated the official unveiling of the Department of Energy (DOE) Summit supercomputer toda Read more…

By Tiffany Trader

New Deep Learning Algorithm Solves Rubik’s Cube

July 25, 2018

Solving (and attempting to solve) Rubik’s Cube has delighted millions of puzzle lovers since 1974 when the cube was invented by Hungarian sculptor and archite Read more…

By John Russell

House Passes $1.275B National Quantum Initiative

September 17, 2018

Last Thursday the U.S. House of Representatives passed the National Quantum Initiative Act (NQIA) intended to accelerate quantum computing research and developm Read more…

By John Russell

AMD’s EPYC Road to Redemption in Six Slides

June 21, 2018

A year ago AMD returned to the server market with its EPYC processor line. The earth didn’t tremble but folks took notice. People remember the Opteron fondly Read more…

By John Russell

Leading Solution Providers

SC17 Booth Video Tours Playlist

Altair @ SC17


AMD @ SC17


ASRock Rack @ SC17

ASRock Rack



DDN Storage @ SC17

DDN Storage

Huawei @ SC17


IBM @ SC17


IBM Power Systems @ SC17

IBM Power Systems

Intel @ SC17


Lenovo @ SC17


Mellanox Technologies @ SC17

Mellanox Technologies

Microsoft @ SC17


Penguin Computing @ SC17

Penguin Computing

Pure Storage @ SC17

Pure Storage

Supericro @ SC17


Tyan @ SC17


Univa @ SC17


Summit Supercomputer is Already Making its Mark on Science

September 20, 2018

Summit, now the fastest supercomputer in the world, is quickly making its mark in science – five of the six finalists just announced for the prestigious 2018 Read more…

By John Russell

Sandia to Take Delivery of World’s Largest Arm System

June 18, 2018

While the enterprise remains circumspect on prospects for Arm servers in the datacenter, the leadership HPC community is taking a bolder, brighter view of the x86 server CPU alternative. Amongst current and planned Arm HPC installations – i.e., the innovative Mont-Blanc project, led by Bull/Atos, the 'Isambard’ Cray XC50 going into the University of Bristol, and commitments from both Japan and France among others -- HPE is announcing that it will be supply the United States National Nuclear Security Administration (NNSA) with a 2.3 petaflops peak Arm-based system, named Astra. Read more…

By Tiffany Trader

D-Wave Breaks New Ground in Quantum Simulation

July 16, 2018

Last Friday D-Wave scientists and colleagues published work in Science which they say represents the first fulfillment of Richard Feynman’s 1982 notion that Read more…

By John Russell

MLPerf – Will New Machine Learning Benchmark Help Propel AI Forward?

May 2, 2018

Let the AI benchmarking wars begin. Today, a diverse group from academia and industry – Google, Baidu, Intel, AMD, Harvard, and Stanford among them – releas Read more…

By John Russell

TACC’s ‘Frontera’ Supercomputer Expands Horizon for Extreme-Scale Science

August 29, 2018

The National Science Foundation and the Texas Advanced Computing Center announced today that a new system, called Frontera, will overtake Stampede 2 as the fast Read more…

By Tiffany Trader

Intel Announces Cooper Lake, Advances AI Strategy

August 9, 2018

Intel's chief datacenter exec Navin Shenoy kicked off the company's Data-Centric Innovation Summit Wednesday, the day-long program devoted to Intel's datacenter Read more…

By Tiffany Trader

GPUs Power Five of World’s Top Seven Supercomputers

June 25, 2018

The top 10 echelon of the newly minted Top500 list boasts three powerful new systems with one common engine: the Nvidia Volta V100 general-purpose graphics proc Read more…

By Tiffany Trader

The Machine Learning Hype Cycle and HPC

June 14, 2018

Like many other HPC professionals I’m following the hype cycle around machine learning/deep learning with interest. I subscribe to the view that we’re probably approaching the ‘peak of inflated expectation’ but not quite yet starting the descent into the ‘trough of disillusionment. This still raises the probability that... Read more…

By Dairsie Latimer

  • arrow
  • Click Here for More Headlines
  • arrow
Do NOT follow this link or you will be banned from the site!
Share This