In a show of strength leading up to ISC the OpenACC standards group today announced its first OpenPOWER implementation, the addition of three new members – University of Illinois, Brookhaven National Laboratory, and Stony Brook University – and details of its expanding 2016 training schedule. Michael Wolfe, technical director of OpenACC, also talked with HPCwire about thorny compiler challenges still remaining as the number of processor (all types) cores grows and memory management issues become more complex.
Currently in private beta testing and planned for public beta in August, the PGI OpenACC compiler supporting OpenPOWER has made steady progress according to Wolfe, who is also a compiler engineer with PGI (NVIDIA). “It includes the same command line. You can take an application, you copy all the sources, all the make files over, just type make, and it builds on the new system,” said Wolfe.
OpenACC (Open Accelerators) is the directives-based programming standard for parallel computing developed by Cray, Nvidia and PGI. The standard is designed to simplify parallel programming of heterogeneous CPU/GPU systems. As in OpenMP, the programmer can annotate C, C++ and Fortran source code to identify the areas that should be accelerated using compiler directives and additional functions. Like OpenMP 4.0 and newer, code can be started on both the CPU and GPU.[i]
The forthcoming version of PGI OpenACC compiler with OpenPOWER will feature:
- Feature parity with PGI Compilers on Linux/x86+Tesla
- CUDA Fortran, OpenACC, OpenMP, CUDA C/C++ host compiler
- Integrated with IBM’s optimized LLVM OpenPOWER code generator
- Write Once, Compile and Run Anywhere
“They way we have implemented this is to use PGI front end and PGI optimizer, and tie it into an LLVM back end code generator. We had support from IBM which has done a lot of work on LLVM and on the code generator and libraries. We were able to leverage a lot of that work,” said Wolfe
The current generation of IBM POWER chip is POWER8+, and Big Blue has said POWER9 processors will likely be ready sometime in 2017. Wolfe isn’t expecting major compatibility issues for the OpenACC compiler.
“Micro-architecturally I’m sure there will be difference in gates and layout and logic design, but from in instruction set perspective I don’t know how much difference [well see]. Typically it’s just additions, new instructions for behavior. Intel does things like double the length of the SIMD (single instruction, multiple data) register. I don’t know if IBM has plans for that.
“There will be versions of POWER8 with the CAPI interface and we’ll be able to work with NVLINK and I think that will be in all the POWER9s. Will it be compatible and will it be optimized for it is the other questions. The thing that we would hope is for the most part that the LLVM code generator will have the low level optimizing for that,” Wolfe said.
The additions of the University of Illinois, Brookhaven, and Stony Brook demonstrate the growing traction of OpenACC said Duncan Poole, director of strategic alliance for the accelerated computing group at NVIDIA and OpenACC president. He noted the value of OpenACC’s various training events (hackathons, workshops, etc) as an important force in attracting new members and sometimes presenting opportunities for computer scientists to publish their work.
“A hackathon that ran at the NCSA (National Center for Supercomputer Applications) brought the University of Illinois into to the fold. Brookhaven participated in a separate hackathon – it’s known for expertise in QCD (quantum chromodynamics) and has a particular library, Grid QCD, which is C++ code. C++ tends to stress the directives model of compilers so having them involved, providing feedback to us as to how we should change the standard and working with them to help migrate their code to OpenACC was important. They see the value and we see the value,” said Poole.
“UIUC joined OpenACC to support two key grants and projects from the NSF/NCSA and DOE that involve scientific research using complex, un-optimized code,” said John Larson, research scientist at the University of Illinois, Urbana-Champaign. “Being a member of the OpenACC standard organization will give both projects early access to technical features of the developing OpenACC language and also enable input that may influence new OpenACC language features.”
OpenACC has held five events in the last 14 months. Three more OpenACC hackathons are planned for the second half of 2016 at the Swiss Supercomputing Center (CSCS), CSC in Helsinki, Finland and the Oak Ridge National Lab. Hackathons are intensive five day hands-on coding sessions intended to help scientists parallelize their applications to run on accelerators and multi- core processors.
In the hackathons, teams (2-6 persons) are paired with experts from OpenACC community. “Very significantly that includes a compiler engineer. The immediate benefit from this is when you run into problems, the [first] thing that the developer asks is, “is it my code that caused the problem or something else.” Early on there were lots of bugs in the compiler but more recently, that hasn’t been the issue, it’s been more understanding the steps you take parallelize code,” said Poole
The first two steps, which Poole said they prefer teams have done before the hackathon, are to settle on their particular compiler of choice and to profile the code to identify where the opportunities for speed-up are. “But it’s not always the case. You basically go through the act of inserting directives to make your code parallel and the next step would be to insert the data directives that help describe data movement between host and the accelerator.”
The events are not designed to “ram OpenACC down everybody’s throat. Even in the hackathon it’s much more a use whatever tool is most appropriate to move your code forward. So it could be math libraries, it could be CUDA, OpenACC, OpenCL, whatever makes sense to the developer,” said Poole.
Poole agrees the term workshop is often used broadly. OpenACC has a fairly specific view of its events: training courses (~two days); workshops (~three days); hackathons (~four days); and academic workshops (~5 days). They vary in scale and duration (see list of upcoming events below).
Academic workshops are the most rigorous. “We do two of these a year right now. The one at ISC this year – (International Workshop on Performance Portable Programming Models for Accelerators (P3MA) with keynoter Simon Hammond of Sandia) – is an academic event: you submit your proposal for the paper you want to have published; it’s peer reviewed by other academics; the top one are selected and presented at the workshop. It’s a proper opportunity to publish for computer scientists,” said Poole
Given the rapid change in the accelerator and processor landscape Poole and Wolfe agree significant challenges remain in efforts to parallelize code and enhance performance and portability. Wolf noted three ongoing issues.
General cleanup is one. “To be frank, the people who wrote the spec, and I mean me and others, don’t really write specifications for a living. We write what we think is correct but sometimes you are not quite as precise as you need be. Sometimes it’s an error but sometimes it’s an assumption that the person reading doesn’t have assumption in mind. So there’s some things in here about the way things are specified – one would be the reduction clause and whether it’s a data clause or not. In OpenACC, it’s not with the data clauses but it has some of the behavior of a data clauses so there’s some clean up that we need to make sure we have things specified properly,” he said.
Multiple device support is the second and one of the bigger headaches, said Wolfe. “Mateo Swiss, for example, bought a system where every node has got a dual socket Haswell (Intel) and eight K80s (see HPCwire article, Europe’s Fastest Supercomputer to get Pascal GPU Upgrade). How do you take advantage of that in a language like OpenACC where you really just want to say here’s a parallel loop, run it across all my resources. That’s a challenge on systems with separate memories. How are you going to manage the memory coherence and allocation with the data computation and data memory? How will you keep the K80s fed.”
Deep Memory is another difficult bottleneck. “If you have deep dynamic structures, multiply linked and nested with their data structures, and you want to move the whole structure over to the device, that’s a specific situation where you have got system memory and device memory and move data from one to the other. We have several different memory pools with different characteristics. With Xeon Phi, for example, you’ve got system memory and multichannel DRAM, high bandwidth memory. Some of these nodes are going to have you system memory in NVRAM and we don’t know quite what the characteristics of that will be but the plan I’m seeing is that it’s byte addressable,” said Wolfe.
“I’ve seen slides – but no circuit design – showing an AMD design where they have APU and CPU cores on chip and multiple types of memory attached – large system memory and a smaller high bandwidth memory – and all of these memories are exposed. They are not managed by the system, not managed by the hardware like a cache; it’s managed by the application. Were trying to see whether and how to manage this in the runtime [by] putting in some data directive that specifies characteristics of the program. I think it’s going to be a significant challenge because we never had a lot of experience with that. It’s not just changing he way you express parallelism, now it changing the memory management as well,” he said.
Challenges aside, OpenACC is working and working well say both Wolfe and Poole. As part of the announcement today, OpenACC cites a 2.5X speedup and significant power reduction on NekCEM (Nekton for Computational Electromagnetics) code achieved at Argonne Leadership Computing Facility.