OpenACC Adds Support for OpenPOWER; Touts Growing Traction

By John Russell

June 13, 2016

In a show of strength leading up to ISC the OpenACC standards group today announced its first OpenPOWER implementation, the addition of three new members – University of Illinois, Brookhaven National Laboratory, and Stony Brook University – and details of its expanding 2016 training schedule. Michael Wolfe, technical director of OpenACC, also talked with HPCwire about thorny compiler challenges still remaining as the number of processor (all types) cores grows and memory management issues become more complex.

Currently in private beta testing and planned for public beta in August, the PGI OpenACC compiler supporting OpenPOWER has made steady progress according to Wolfe, who is also a compiler engineer with PGI (NVIDIA). “It includes the same command line. You can take an application, you copy all the sources, all the make files over, just type make, and it builds on the new system,” said Wolfe.

OpenACC (Open Accelerators) is the directives-based programming standard for parallel computing developed by Cray, Nvidia and PGI. The standard is designed to simplify parallel programming of heterogeneous CPU/GPU systems. As in OpenMP, the programmer can annotate C, C++ and Fortran source code to identify the areas that should be accelerated using compiler directives and additional functions. Like OpenMP 4.0 and newer, code can be started on both the CPU and GPU.[i]

The forthcoming version of PGI OpenACC compiler with OpenPOWER will feature:

  • Feature parity with PGI Compilers on Linux/x86+Tesla
  • CUDA Fortran, OpenACC, OpenMP, CUDA C/C++ host compiler
  • Integrated with IBM’s optimized LLVM OpenPOWER code generator
  • Write Once, Compile and Run Anywhere

“They way we have implemented this is to use PGI front end and PGI optimizer, and tie it into an LLVM back end code generator. We had support from IBM which has done a lot of work on LLVM and on the code generator and libraries. We were able to leverage a lot of that work,” said Wolfe

The current generation of IBM POWER chip is POWER8+, and Big Blue has said POWER9 processors will likely be ready sometime in 2017. Wolfe isn’t expecting major compatibility issues for the OpenACC compiler.

“Micro-architecturally I’m sure there will be difference in gates and layout and logic design, but from in instruction set perspective I don’t know how much difference [well see]. Typically it’s just additions, new instructions for behavior. Intel does things like double the length of the SIMD (single instruction, multiple data) register. I don’t know if IBM has plans for that.

“There will be versions of POWER8 with the CAPI interface and we’ll be able to work with NVLINK and I think that will be in all the POWER9s. Will it be compatible and will it be optimized for it is the other questions. The thing that we would hope is for the most part that the LLVM code generator will have the low level optimizing for that,” Wolfe said.

OpenACC.OpenPOWER Support

The additions of the University of Illinois, Brookhaven, and Stony Brook demonstrate the growing traction of OpenACC said Duncan Poole, director of strategic alliance for the accelerated computing group at NVIDIA and OpenACC president. He noted the value of OpenACC’s various training events (hackathons, workshops, etc) as an important force in attracting new members and sometimes presenting opportunities for computer scientists to publish their work.

“A hackathon that ran at the NCSA (National Center for Supercomputer Applications) brought the University of Illinois into to the fold. Brookhaven participated in a separate hackathon – it’s known for expertise in QCD (quantum chromodynamics) and has a particular library, Grid QCD, which is C++ code. C++ tends to stress the directives model of compilers so having them involved, providing feedback to us as to how we should change the standard and working with them to help migrate their code to OpenACC was important. They see the value and we see the value,” said Poole.

“UIUC joined OpenACC to support two key grants and projects from the NSF/NCSA and DOE that involve scientific research using complex, un-optimized code,” said John Larson, research scientist at the University of Illinois, Urbana-Champaign. “Being a member of the OpenACC standard organization will give both projects early access to technical features of the developing OpenACC language and also enable input that may influence new OpenACC language features.”

OpenACC has held five events in the last 14 months. Three more OpenACC hackathons are planned for the second half of 2016 at the Swiss Supercomputing Center (CSCS), CSC in Helsinki, Finland and the Oak Ridge National Lab. Hackathons are intensive five day hands-on coding sessions intended to help scientists parallelize their applications to run on accelerators and multi- core processors.

In the hackathons, teams (2-6 persons) are paired with experts from OpenACC community. “Very significantly that includes a compiler engineer. The immediate benefit from this is when you run into problems, the [first] thing that the developer asks is, “is it my code that caused the problem or something else.” Early on there were lots of bugs in the compiler but more recently, that hasn’t been the issue, it’s been more understanding the steps you take parallelize code,” said Poole

The first two steps, which Poole said they prefer teams have done before the hackathon, are to settle on their particular compiler of choice and to profile the code to identify where the opportunities for speed-up are. “But it’s not always the case. You basically go through the act of inserting directives to make your code parallel and the next step would be to insert the data directives that help describe data movement between host and the accelerator.”

The events are not designed to “ram OpenACC down everybody’s throat. Even in the hackathon it’s much more a use whatever tool is most appropriate to move your code forward. So it could be math libraries, it could be CUDA, OpenACC, OpenCL, whatever makes sense to the developer,” said Poole.

Poole agrees the term workshop is often used broadly. OpenACC has a fairly specific view of its events: training courses (~two days); workshops (~three days); hackathons (~four days); and academic workshops (~5 days). They vary in scale and duration (see list of upcoming events below).

Academic workshops are the most rigorous. “We do two of these a year right now. The one at ISC this year – (International Workshop on Performance Portable Programming Models for Accelerators (P3MA) with keynoter Simon Hammond of Sandia) – is an academic event: you submit your proposal for the paper you want to have published; it’s peer reviewed by other academics; the top one are selected and presented at the workshop. It’s a proper opportunity to publish for computer scientists,” said Poole

OpenACC Hackathons

Given the rapid change in the accelerator and processor landscape Poole and Wolfe agree significant challenges remain in efforts to parallelize code and enhance performance and portability. Wolf noted three ongoing issues.

General cleanup is one. “To be frank, the people who wrote the spec, and I mean me and others, don’t really write specifications for a living. We write what we think is correct but sometimes you are not quite as precise as you need be. Sometimes it’s an error but sometimes it’s an assumption that the person reading doesn’t have assumption in mind. So there’s some things in here about the way things are specified – one would be the reduction clause and whether it’s a data clause or not. In OpenACC, it’s not with the data clauses but it has some of the behavior of a data clauses so there’s some clean up that we need to make sure we have things specified properly,” he said.

Multiple device support is the second and one of the bigger headaches, said Wolfe. “Mateo Swiss, for example, bought a system where every node has got a dual socket Haswell (Intel) and eight K80s (see HPCwire article, Europe’s Fastest Supercomputer to get Pascal GPU Upgrade). How do you take advantage of that in a language like OpenACC where you really just want to say here’s a parallel loop, run it across all my resources. That’s a challenge on systems with separate memories. How are you going to manage the memory coherence and allocation with the data computation and data memory? How will you keep the K80s fed.”

Deep Memory is another difficult bottleneck. “If you have deep dynamic structures, multiply linked and nested with their data structures, and you want to move the whole structure over to the device, that’s a specific situation where you have got system memory and device memory and move data from one to the other. We have several different memory pools with different characteristics. With Xeon Phi, for example, you’ve got system memory and multichannel DRAM, high bandwidth memory. Some of these nodes are going to have you system memory in NVRAM and we don’t know quite what the characteristics of that will be but the plan I’m seeing is that it’s byte addressable,” said Wolfe.

“I’ve seen slides – but no circuit design – showing an AMD design where they have APU and CPU cores on chip and multiple types of memory attached – large system memory and a smaller high bandwidth memory – and all of these memories are exposed. They are not managed by the system, not managed by the hardware like a cache; it’s managed by the application. Were trying to see whether and how to manage this in the runtime [by] putting in some data directive that specifies characteristics of the program. I think it’s going to be a significant challenge because we never had a lot of experience with that. It’s not just changing he way you express parallelism, now it changing the memory management as well,” he said.

Challenges aside, OpenACC is working and working well say both Wolfe and Poole. As part of the announcement today, OpenACC cites a 2.5X speedup and significant power reduction on NekCEM (Nekton for Computational Electromagnetics) code achieved at Argonne Leadership Computing Facility.

OpenACC.NekCEM

[i] https://en.wikipedia.org/wiki/OpenACC

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

Talk to Me: Nvidia Claims NLP Inference, Training Records

August 15, 2019

Nvidia says it’s achieved significant advances in conversation natural language processing (NLP) training and inference, enabling more complex, immediate-response interchanges between customers and chatbots. And the co Read more…

By Doug Black

Trump Administration and NIST Issue AI Standards Development Plan

August 14, 2019

Efforts to develop AI are gathering steam fast. On Monday, the White House issued a federal plan to help develop technical standards for AI following up on a mandate contained in the Administration’s AI Executive Order Read more…

By John Russell

Scientists to Tap Exascale Computing to Unlock the Mystery of our Accelerating Universe

August 14, 2019

The universe and everything in it roared to life with the Big Bang approximately 13.8 billion years ago. It has continued expanding ever since. While we have a good understanding of the early universe, its fate billions Read more…

By Rob Johnson

AWS Solution Channel

Efficiency and Cost-Optimization for HPC Workloads – AWS Batch and Amazon EC2 Spot Instances

High Performance Computing on AWS leverages the power of cloud computing and the extreme scale it offers to achieve optimal HPC price/performance. With AWS you can right size your services to meet exactly the capacity requirements you need without having to overprovision or compromise capacity. Read more…

HPE Extreme Performance Solutions

Bring the combined power of HPC and AI to your business transformation

FPGA (Field Programmable Gate Array) acceleration cards are not new, as they’ve been commercially available since 1984. Typically, the emphasis around FPGAs has centered on the fact that they’re programmable accelerators, and that they can truly offer workload specific hardware acceleration solutions without requiring custom silicon. Read more…

IBM Accelerated Insights

Cloudy with a Chance of Mainframes

[Connect with HPC users and learn new skills in the IBM Spectrum LSF User Community.]

Rapid rates of change sometimes result in unexpected bedfellows. Read more…

Argonne Supercomputer Accelerates Cancer Prediction Research

August 13, 2019

In the fight against cancer, early prediction, which drastically improves prognoses, is critical. Now, new research by a team from Northwestern University – and accelerated by supercomputing resources at Argonne Nation Read more…

By Oliver Peckham

Scientists to Tap Exascale Computing to Unlock the Mystery of our Accelerating Universe

August 14, 2019

The universe and everything in it roared to life with the Big Bang approximately 13.8 billion years ago. It has continued expanding ever since. While we have a Read more…

By Rob Johnson

AI is the Next Exascale – Rick Stevens on What that Means and Why It’s Important

August 13, 2019

Twelve years ago the Department of Energy (DOE) was just beginning to explore what an exascale computing program might look like and what it might accomplish. Today, DOE is repeating that process for AI, once again starting with science community town halls to gather input and stimulate conversation. The town hall program... Read more…

By Tiffany Trader and John Russell

Cray Wins NNSA-Livermore ‘El Capitan’ Exascale Contract

August 13, 2019

Cray has won the bid to build the first exascale supercomputer for the National Nuclear Security Administration (NNSA) and Lawrence Livermore National Laborator Read more…

By Tiffany Trader

AMD Launches Epyc Rome, First 7nm CPU

August 8, 2019

From a gala event at the Palace of Fine Arts in San Francisco yesterday (Aug. 7), AMD launched its second-generation Epyc Rome x86 chips, based on its 7nm proce Read more…

By Tiffany Trader

Lenovo Drives Single-Socket Servers with AMD Epyc Rome CPUs

August 7, 2019

No summer doldrums here. As part of the AMD Epyc Rome launch event in San Francisco today, Lenovo announced two new single-socket servers, the ThinkSystem SR635 Read more…

By Doug Black

Building Diversity and Broader Engagement in the HPC Community

August 7, 2019

Increasing diversity and inclusion in HPC is a community-building effort. Representation of both issues and individuals matters - the more people see HPC in a w Read more…

By AJ Lauer

Xilinx vs. Intel: FPGA Market Leaders Launch Server Accelerator Cards

August 6, 2019

The two FPGA market leaders, Intel and Xilinx, both announced new accelerator cards this week designed to handle specialized, compute-intensive workloads and un Read more…

By Doug Black

Upcoming NSF Cyberinfrastructure Projects to Support ‘Long-Tail’ Users, AI and Big Data

August 5, 2019

The National Science Foundation is well positioned to support national priorities, as new NSF-funded HPC systems to come online in the upcoming year promise to Read more…

By Ken Chiacchia, Pittsburgh Supercomputing Center/XSEDE

High Performance (Potato) Chips

May 5, 2006

In this article, we focus on how Procter & Gamble is using high performance computing to create some common, everyday supermarket products. Tom Lange, a 27-year veteran of the company, tells us how P&G models products, processes and production systems for the betterment of consumer package goods. Read more…

By Michael Feldman

Supercomputer-Powered AI Tackles a Key Fusion Energy Challenge

August 7, 2019

Fusion energy is the Holy Grail of the energy world: low-radioactivity, low-waste, zero-carbon, high-output nuclear power that can run on hydrogen or lithium. T Read more…

By Oliver Peckham

Cray, AMD to Extend DOE’s Exascale Frontier

May 7, 2019

Cray and AMD are coming back to Oak Ridge National Laboratory to partner on the world’s largest and most expensive supercomputer. The Department of Energy’s Read more…

By Tiffany Trader

Graphene Surprises Again, This Time for Quantum Computing

May 8, 2019

Graphene is fascinating stuff with promise for use in a seeming endless number of applications. This month researchers from the University of Vienna and Institu Read more…

By John Russell

AMD Verifies Its Largest 7nm Chip Design in Ten Hours

June 5, 2019

AMD announced last week that its engineers had successfully executed the first physical verification of its largest 7nm chip design – in just ten hours. The AMD Radeon Instinct Vega20 – which boasts 13.2 billion transistors – was tested using a TSMC-certified Calibre nmDRC software platform from Mentor. Read more…

By Oliver Peckham

TSMC and Samsung Moving to 5nm; Whither Moore’s Law?

June 12, 2019

With reports that Taiwan Semiconductor Manufacturing Co. (TMSC) and Samsung are moving quickly to 5nm manufacturing, it’s a good time to again ponder whither goes the venerable Moore’s law. Shrinking feature size has of course been the primary hallmark of achieving Moore’s law... Read more…

By John Russell

Deep Learning Competitors Stalk Nvidia

May 14, 2019

There is no shortage of processing architectures emerging to accelerate deep learning workloads, with two more options emerging this week to challenge GPU leader Nvidia. First, Intel researchers claimed a new deep learning record for image classification on the ResNet-50 convolutional neural network. Separately, Israeli AI chip startup Hailo.ai... Read more…

By George Leopold

Nvidia Embraces Arm, Declares Intent to Accelerate All CPU Architectures

June 17, 2019

As the Top500 list was being announced at ISC in Frankfurt today with an upgraded petascale Arm supercomputer in the top third of the list, Nvidia announced its Read more…

By Tiffany Trader

Leading Solution Providers

ISC 2019 Virtual Booth Video Tour

CRAY
CRAY
DDN
DDN
DELL EMC
DELL EMC
GOOGLE
GOOGLE
ONE STOP SYSTEMS
ONE STOP SYSTEMS
PANASAS
PANASAS
VERNE GLOBAL
VERNE GLOBAL

Cray Wins NNSA-Livermore ‘El Capitan’ Exascale Contract

August 13, 2019

Cray has won the bid to build the first exascale supercomputer for the National Nuclear Security Administration (NNSA) and Lawrence Livermore National Laborator Read more…

By Tiffany Trader

Top500 Purely Petaflops; US Maintains Performance Lead

June 17, 2019

With the kick-off of the International Supercomputing Conference (ISC) in Frankfurt this morning, the 53rd Top500 list made its debut, and this one's for petafl Read more…

By Tiffany Trader

A Behind-the-Scenes Look at the Hardware That Powered the Black Hole Image

June 24, 2019

Two months ago, the first-ever image of a black hole took the internet by storm. A team of scientists took years to produce and verify the striking image – an Read more…

By Oliver Peckham

Cray – and the Cray Brand – to Be Positioned at Tip of HPE’s HPC Spear

May 22, 2019

More so than with most acquisitions of this kind, HPE’s purchase of Cray for $1.3 billion, announced last week, seems to have elements of that overused, often Read more…

By Doug Black and Tiffany Trader

AMD Launches Epyc Rome, First 7nm CPU

August 8, 2019

From a gala event at the Palace of Fine Arts in San Francisco yesterday (Aug. 7), AMD launched its second-generation Epyc Rome x86 chips, based on its 7nm proce Read more…

By Tiffany Trader

Chinese Company Sugon Placed on US ‘Entity List’ After Strong Showing at International Supercomputing Conference

June 26, 2019

After more than a decade of advancing its supercomputing prowess, operating the world’s most powerful supercomputer from June 2013 to June 2018, China is keep Read more…

By Tiffany Trader

In Wake of Nvidia-Mellanox: Xilinx to Acquire Solarflare

April 25, 2019

With echoes of Nvidia’s recent acquisition of Mellanox, FPGA maker Xilinx has announced a definitive agreement to acquire Solarflare Communications, provider Read more…

By Doug Black

Qualcomm Invests in RISC-V Startup SiFive

June 7, 2019

Investors are zeroing in on the open standard RISC-V instruction set architecture and the processor intellectual property being developed by a batch of high-flying chip startups. Last fall, Esperanto Technologies announced a $58 million funding round. Read more…

By George Leopold

  • arrow
  • Click Here for More Headlines
  • arrow
Do NOT follow this link or you will be banned from the site!
Share This