Intel Launches ‘Knights Landing’ Phi Family for HPC, Machine Learning

By Tiffany Trader

June 21, 2016

From ISC 2016 in Frankfurt, Germany, this week, Intel Corp. launched the second-generation Xeon Phi product family, formerly code-named Knights Landing, aimed at HPC and machine learning workloads. The company had been shipping “Knights Landing” silicon to early customers for the last six months and was waiting to ramp up production before making the product generally available.

The window also gave OEMs time to complete their readiness, said Intel’s Charlie Wuischpard, vice president of the Data Center Group and general manager of High Performance Computing Platform Group, in a media pre-briefing. Those OEMs include the usual names: Cray, HPE, Lenovo, Dell and others.

The most distinguishing feature of the chip is that it’s a bootable host CPU — unlike its predecessor “Knights Corner,” which is a coprocessor that connects over PCIe. “We’re not just a specialized programming model,” said Intel’s General Manager, HPC Compute and Networking, Barry Davis in a hand-on technical demo held at ISC. “We’re the full IA programming model. There’s no PCIe bottleneck; there’s a limitation in the data that you can send back and forth from the host CPU to the accelerator or coprocessor and we removed that bottleneck.”

The “Knights Landing” Phi will be the first chip to offer an integrated fabric, Intel’s Omni-Path Architecture (OPA), in the package. “Knights Landing” also puts integrated on-package memory in a processor, which benefits memory bandwidth and overall application performance. A six-channel memory controller supports up to 384 GB of DDR4-2400 memory (~90GB/s sustained bandwidth). There are 36 PCI Express 3.0 lanes for connecting to PCIe coprocessors, PCIe SSDs or discrete graphics cards.

The second-generation Phi is based on an Intel Atom core (based on the Silvermont microarchitecture) with many HPC enhancements. The MIC (Many Integrated Cores) design fits 8 billion transistors on a die, using 14 nm process technology. The new Phi family introduces the AVX-512 instruction set, which will be available on future Xeon processors. Both the Phi and the Xeon are binary compatible and a benefit of this is that the optimizations that apply to one platform typically carry to the other, notes Intel.

Intel emphasizes that the Phi is designed to run any workload, any IA code. “There are workloads out there that are single thread that maybe benefit from higher frequency and fewer cores and of course you would run those on a Xeon but it doesn’t mean those applications won’t still run on a Xeon Phi,” said Wuischpard. “Some of our early customers are implementing an entire supercomputing cluster with Xeon Phi. Others are doing a mix of Xeon and Xeon Phi and there are a lot of configurations that are possible within a given system deployment.”

As previously announced, the Phi product family comes in three variants: a PCIe coprocessor form factor; a stand-alone CPU; and a stand-alone CPU with integrated Omni-Path fabric technology. The SKU stack that Intel is launching includes four parts with different core counts, frequencies, TDPs and price points.

There are three parts shipping now: the 68-core 7250 (1.4 Ghz), the 64-core 7230 (1.3 Ghz) and the 64-core 7210 (1.3 Ghz). The TDP on all of these is 215 watts. The top-bin part – the Xeon Phi 7290 – is the promised 72-core version. The $6,250 SKU runs at 1.5 Ghz and consumes 245 watts of power; it will not be available until September. Integrated fabric versions of all four parts will not be available until October. Powering the fabric will add another 15 watts to the TDP envelope. The coprocessor card will be available in the second half the year, according to Intel.

Intel KNL Phi SKU list

“You can think of it as the 7200-series Xeon processor,” said Wuischpard, “You’ll see that all of the memory is 16 GBs across the board. We had originally talked about having a richer matrix of SKUs that ranged from no in-package memory to 16 GB of memory and then across these ranges of performance and it just looked too busy and too complex, and in the end everyone wants that in-package memory so we decided to shrink the SKU stack and make it easier to understand. And it does make it easier from a manufacturing perspective.”

The Xeon 7290 is a premium product with a premium price. This is by design since it’s relatively low-yielding, according to Intel. “Most of our early customers and this includes the large research labs and institutions have really focused on the 7230 and the 7250 to get the best price/performance. And we expect the 7210 will be the more general purpose high-running part,” said Wuishpard, adding that it offers 85-90 percent of the performance at less than half the price of the top-end part.

The self-hosted Phi processor competes directly with Tesla GPUs from Nvidia with both products targeting HPC and machine learning and visualization. At its GTC16 event, NVIDIA announced the NVLink-based Pascal GPU. The NVLink point-to-point interconnect’s advantage is enabling data sharing at rates five to 12 times faster than traditional PCI Express Gen 3.0. Currently, the NVLink-based P100 is only available to customers who shell out the $129,000 for NVIDIA’s “deep learning supercomputer,” the DGX-1, but the standalone NVLink-based P100 is expected to hit production availability early 2017.

Intel talks about scalability as being a big difference between a GPU card and Xeon Phi. “With GPU cards, you can only put so many cards in a box,” says Intel’s Barry Davis. “Even with NV-LINK to connect those together, you are still limited in that scale. As you look at the Xeon Phi product line with implementations at thousands of nodes, scalability is a key part of this architecture, and that’s what the market needs today, whether you are talking about machine learning, deep learning or traditional modeling and simulation.”

When it comes to artificial intelligence and deep learning, Intel has published several initial benchmarks claiming performance improvements over GPUs on a number of machine learning workloads.

Intel KNL Phi deep learning-1400x

NVIDIA’s VP, Solutions Architecture and Engineering, Marc Hamilton, said he questions the benchmarks that Intel has released so far, noting that the claims relating to deep learning were done against older versions of GPUs (Kepler) using unoptimized versions of frameworks. [The benchmark breakdown was unavailable on Intel’s site as of press time.] Hamilton also said that the “Knights Landing” does not have the strong node capability of the GPU. NVIDIA GPUs currently scale to 8-way configurations, but the OS will support 16 (recall the K80 has two physical GPUs inside it and the OS will support 8 of these).

There’s also a performance difference between the second-generation Phi and the newest Tesla GPUs. The top bin Knights Landing Phi CPU delivers 3.46 teraflops of double-precision floating point performance. The Pascal P100 GPU for NVLink-optimized servers offers 5.3 teraflops of double-precision floating point performance, and the PCIe version supports 4.7 teraflops of double-precision.

One early customer who has already deployed a Knights Landing Phi-based system is the Texas Advanced Computing Center (TACC) at the University of Austin at Texas. TACC got the 508 node system – an interim step between Stampede 1 and Stampede 2 – up and running and benchmarked on LINPACK three days after receiving its racks.

TACC Director Dan Stanzione wryly commented that that is not his preferred timeframe, but the result was a 117th place ranking on the latest TOP500 with a LINPACK of 817.8 teraflops. “Obviously the software came up pretty quickly in order to make that happen,” said Stanzione.

“We finished all of our benchmarking,” he continued, “and we’re putting users on it this week and are running our first tutorial on Sunday here at ISC.” The system employs the top-bin-minus-1 68-core Xeon Phi 7250 processor and the Omni-Path fabric.

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

HPC in Life Sciences Part 1: CPU Choices, Rise of Data Lakes, Networking Challenges, and More

February 21, 2019

For the past few years HPCwire and leaders of BioTeam, a research computing consultancy specializing in life sciences, have convened to examine the state of HPC (and now AI) use in life sciences. Without HPC writ large, modern life sciences research would quickly grind to a halt. It’s true most life sciences research computing... Read more…

By John Russell

Arm Unveils Neoverse N1 Platform with up to 128-Cores

February 20, 2019

Following on its Neoverse roadmap announcement last October, Arm today revealed its next-gen Neoverse microarchitecture with compute and throughput-optimized silicon designs catered toward general-purpose cloud computing Read more…

By Tiffany Trader

The Internet of Criminal Things—Trust in the Gods but Verify!

February 20, 2019

“Are we under attack?” asked Professor Elmarie Biermann of the Cyber Security Institute during the recent South African Centre for High Performance Computing’s (CHPC) National Conference in Cape Town. A quick show Read more…

By Elizabeth Leake, STEM-Trek

HPE Extreme Performance Solutions

HPE and Intel® Omni-Path Architecture: How to Power a Cloud

Learn how HPE and Intel® Omni-Path Architecture provide critical infrastructure for leading Nordic HPC provider’s HPCFLOW cloud service.

powercloud_blog.jpgFor decades, HPE has been at the forefront of high-performance computing, and we’ve powered some of the fastest and most robust supercomputers in the world. Read more…

IBM Accelerated Insights

The Perils of Becoming Trapped in the Cloud

Terms like ‘open systems’ have been bandied about for decades. While modern computer systems are relatively open compared to their predecessors, there are still plenty of opportunities to become locked into proprietary interfaces. Read more…

Machine Learning Takes Heat for Science’s Reproducibility Crisis

February 19, 2019

Scientists are raising red flags about the accuracy and reproducibility of conclusions drawn by machine learning frameworks. Among the remedies are developing new ML systems that can question their own predictions, show Read more…

By George Leopold

HPC in Life Sciences Part 1: CPU Choices, Rise of Data Lakes, Networking Challenges, and More

February 21, 2019

For the past few years HPCwire and leaders of BioTeam, a research computing consultancy specializing in life sciences, have convened to examine the state of HPC (and now AI) use in life sciences. Without HPC writ large, modern life sciences research would quickly grind to a halt. It’s true most life sciences research computing... Read more…

By John Russell

Arm Unveils Neoverse N1 Platform with up to 128-Cores

February 20, 2019

Following on its Neoverse roadmap announcement last October, Arm today revealed its next-gen Neoverse microarchitecture with compute and throughput-optimized si Read more…

By Tiffany Trader

Insights from Optimized Codes on Cineca’s Marconi

February 15, 2019

What can you do with 381,392 CPU cores? For Cineca, it means enabling computational scientists to expand a large part of the world’s body of knowledge from the nanoscale to the astronomic, from calculating quantum effects in new materials to supporting bioinformatics for advanced healthcare research to screening millions of possible chemical combinations to attack a deadly virus. Read more…

By Ken Strandberg

ClusterVision in Bankruptcy, Fate Uncertain

February 13, 2019

ClusterVision, European HPC specialists that have built and installed over 20 Top500-ranked systems in their nearly 17-year history, appear to be in the midst o Read more…

By Tiffany Trader

UC Berkeley Paper Heralds Rise of Serverless Computing in the Cloud – Do You Agree?

February 13, 2019

Almost exactly ten years to the day from publishing of their widely-read, seminal paper on cloud computing, UC Berkeley researchers have issued another ambitious examination of cloud computing - Cloud Programming Simplified: A Berkeley View on Serverless Computing. The new work heralds the rise of ‘serverless computing’ as the next dominant phase of cloud computing. Read more…

By John Russell

Iowa ‘Grows Its Own’ to Fill the HPC Workforce Pipeline

February 13, 2019

The global workforce that supports advanced computing, scientific software and high-speed research networks is relatively small when you stop to consider the magnitude of the transformative discoveries it empowers. Technical conferences provide a forum where specialists convene to learn about the latest innovations and schedule face-time with colleagues from other institutions. Read more…

By Elizabeth Leake, STEM-Trek

Trump Signs Executive Order Launching U.S. AI Initiative

February 11, 2019

U.S. President Donald Trump issued an Executive Order (EO) today launching a U.S Artificial Intelligence Initiative. The new initiative - Maintaining American L Read more…

By John Russell

Celebrating Women in Science: Meet Four Women Leading the Way in HPC

February 11, 2019

One only needs to look around at virtually any CS/tech conference to realize that women are underrepresented, and that holds true of HPC. SC hosts over 13,000 H Read more…

By AJ Lauer

Quantum Computing Will Never Work

November 27, 2018

Amid the gush of money and enthusiastic predictions being thrown at quantum computing comes a proposed cold shower in the form of an essay by physicist Mikhail Read more…

By John Russell

Cray Unveils Shasta, Lands NERSC-9 Contract

October 30, 2018

Cray revealed today the details of its next-gen supercomputing architecture, Shasta, selected to be the next flagship system at NERSC. We've known of the code-name "Shasta" since the Argonne slice of the CORAL project was announced in 2015 and although the details of that plan have changed considerably, Cray didn't slow down its timeline for Shasta. Read more…

By Tiffany Trader

The Case Against ‘The Case Against Quantum Computing’

January 9, 2019

It’s not easy to be a physicist. Richard Feynman (basically the Jimi Hendrix of physicists) once said: “The first principle is that you must not fool yourse Read more…

By Ben Criger

AMD Sets Up for Epyc Epoch

November 16, 2018

It’s been a good two weeks, AMD’s Gary Silcott and Andy Parma told me on the last day of SC18 in Dallas at the restaurant where we met to discuss their show news and recent successes. Heck, it’s been a good year. Read more…

By Tiffany Trader

Intel Reportedly in $6B Bid for Mellanox

January 30, 2019

The latest rumors and reports around an acquisition of Mellanox focus on Intel, which has reportedly offered a $6 billion bid for the high performance interconn Read more…

By Doug Black

ClusterVision in Bankruptcy, Fate Uncertain

February 13, 2019

ClusterVision, European HPC specialists that have built and installed over 20 Top500-ranked systems in their nearly 17-year history, appear to be in the midst o Read more…

By Tiffany Trader

US Leads Supercomputing with #1, #2 Systems & Petascale Arm

November 12, 2018

The 31st Supercomputing Conference (SC) - commemorating 30 years since the first Supercomputing in 1988 - kicked off in Dallas yesterday, taking over the Kay Ba Read more…

By Tiffany Trader

Looking for Light Reading? NSF-backed ‘Comic Books’ Tackle Quantum Computing

January 28, 2019

Still baffled by quantum computing? How about turning to comic books (graphic novels for the well-read among you) for some clarity and a little humor on QC. The Read more…

By John Russell

Leading Solution Providers

SC 18 Virtual Booth Video Tour

Advania @ SC18 AMD @ SC18
ASRock Rack @ SC18
DDN Storage @ SC18
HPE @ SC18
IBM @ SC18
Lenovo @ SC18 Mellanox Technologies @ SC18
NVIDIA @ SC18
One Stop Systems @ SC18
Oracle @ SC18 Panasas @ SC18
Supermicro @ SC18 SUSE @ SC18 TYAN @ SC18
Verne Global @ SC18

Contract Signed for New Finnish Supercomputer

December 13, 2018

After the official contract signing yesterday, configuration details were made public for the new BullSequana system that the Finnish IT Center for Science (CSC Read more…

By Tiffany Trader

Deep500: ETH Researchers Introduce New Deep Learning Benchmark for HPC

February 5, 2019

ETH researchers have developed a new deep learning benchmarking environment – Deep500 – they say is “the first distributed and reproducible benchmarking s Read more…

By John Russell

IBM Quantum Update: Q System One Launch, New Collaborators, and QC Center Plans

January 10, 2019

IBM made three significant quantum computing announcements at CES this week. One was introduction of IBM Q System One; it’s really the integration of IBM’s Read more…

By John Russell

HPC Reflections and (Mostly Hopeful) Predictions

December 19, 2018

So much ‘spaghetti’ gets tossed on walls by the technology community (vendors and researchers) to see what sticks that it is often difficult to peer through Read more…

By John Russell

IBM Bets $2B Seeking 1000X AI Hardware Performance Boost

February 7, 2019

For now, AI systems are mostly machine learning-based and “narrow” – powerful as they are by today's standards, they're limited to performing a few, narro Read more…

By Doug Black

Nvidia’s Jensen Huang Delivers Vision for the New HPC

November 14, 2018

For nearly two hours on Monday at SC18, Jensen Huang, CEO of Nvidia, presented his expansive view of the future of HPC (and computing in general) as only he can do. Animated. Backstopped by a stream of data charts, product photos, and even a beautiful image of supernovae... Read more…

By John Russell

The Deep500 – Researchers Tackle an HPC Benchmark for Deep Learning

January 7, 2019

How do you know if an HPC system, particularly a larger-scale system, is well-suited for deep learning workloads? Today, that’s not an easy question to answer Read more…

By John Russell

Intel Confirms 48-Core Cascade Lake-AP for 2019

November 4, 2018

As part of the run-up to SC18, taking place in Dallas next week (Nov. 11-16), Intel is doling out info on its next-gen Cascade Lake family of Xeon processors, specifically the “Advanced Processor” version (Cascade Lake-AP), architected for high-performance computing, artificial intelligence and infrastructure-as-a-service workloads. Read more…

By Tiffany Trader

  • arrow
  • Click Here for More Headlines
  • arrow
Do NOT follow this link or you will be banned from the site!
Share This