Intel Launches ‘Knights Landing’ Phi Family for HPC, Machine Learning

By Tiffany Trader

June 21, 2016

From ISC 2016 in Frankfurt, Germany, this week, Intel Corp. launched the second-generation Xeon Phi product family, formerly code-named Knights Landing, aimed at HPC and machine learning workloads. The company had been shipping “Knights Landing” silicon to early customers for the last six months and was waiting to ramp up production before making the product generally available.

The window also gave OEMs time to complete their readiness, said Intel’s Charlie Wuischpard, vice president of the Data Center Group and general manager of High Performance Computing Platform Group, in a media pre-briefing. Those OEMs include the usual names: Cray, HPE, Lenovo, Dell and others.

The most distinguishing feature of the chip is that it’s a bootable host CPU — unlike its predecessor “Knights Corner,” which is a coprocessor that connects over PCIe. “We’re not just a specialized programming model,” said Intel’s General Manager, HPC Compute and Networking, Barry Davis in a hand-on technical demo held at ISC. “We’re the full IA programming model. There’s no PCIe bottleneck; there’s a limitation in the data that you can send back and forth from the host CPU to the accelerator or coprocessor and we removed that bottleneck.”

The “Knights Landing” Phi will be the first chip to offer an integrated fabric, Intel’s Omni-Path Architecture (OPA), in the package. “Knights Landing” also puts integrated on-package memory in a processor, which benefits memory bandwidth and overall application performance. A six-channel memory controller supports up to 384 GB of DDR4-2400 memory (~90GB/s sustained bandwidth). There are 36 PCI Express 3.0 lanes for connecting to PCIe coprocessors, PCIe SSDs or discrete graphics cards.

The second-generation Phi is based on an Intel Atom core (based on the Silvermont microarchitecture) with many HPC enhancements. The MIC (Many Integrated Cores) design fits 8 billion transistors on a die, using 14 nm process technology. The new Phi family introduces the AVX-512 instruction set, which will be available on future Xeon processors. Both the Phi and the Xeon are binary compatible and a benefit of this is that the optimizations that apply to one platform typically carry to the other, notes Intel.

Intel emphasizes that the Phi is designed to run any workload, any IA code. “There are workloads out there that are single thread that maybe benefit from higher frequency and fewer cores and of course you would run those on a Xeon but it doesn’t mean those applications won’t still run on a Xeon Phi,” said Wuischpard. “Some of our early customers are implementing an entire supercomputing cluster with Xeon Phi. Others are doing a mix of Xeon and Xeon Phi and there are a lot of configurations that are possible within a given system deployment.”

As previously announced, the Phi product family comes in three variants: a PCIe coprocessor form factor; a stand-alone CPU; and a stand-alone CPU with integrated Omni-Path fabric technology. The SKU stack that Intel is launching includes four parts with different core counts, frequencies, TDPs and price points.

There are three parts shipping now: the 68-core 7250 (1.4 Ghz), the 64-core 7230 (1.3 Ghz) and the 64-core 7210 (1.3 Ghz). The TDP on all of these is 215 watts. The top-bin part – the Xeon Phi 7290 – is the promised 72-core version. The $6,250 SKU runs at 1.5 Ghz and consumes 245 watts of power; it will not be available until September. Integrated fabric versions of all four parts will not be available until October. Powering the fabric will add another 15 watts to the TDP envelope. The coprocessor card will be available in the second half the year, according to Intel.

Intel KNL Phi SKU list

“You can think of it as the 7200-series Xeon processor,” said Wuischpard, “You’ll see that all of the memory is 16 GBs across the board. We had originally talked about having a richer matrix of SKUs that ranged from no in-package memory to 16 GB of memory and then across these ranges of performance and it just looked too busy and too complex, and in the end everyone wants that in-package memory so we decided to shrink the SKU stack and make it easier to understand. And it does make it easier from a manufacturing perspective.”

The Xeon 7290 is a premium product with a premium price. This is by design since it’s relatively low-yielding, according to Intel. “Most of our early customers and this includes the large research labs and institutions have really focused on the 7230 and the 7250 to get the best price/performance. And we expect the 7210 will be the more general purpose high-running part,” said Wuishpard, adding that it offers 85-90 percent of the performance at less than half the price of the top-end part.

The self-hosted Phi processor competes directly with Tesla GPUs from Nvidia with both products targeting HPC and machine learning and visualization. At its GTC16 event, NVIDIA announced the NVLink-based Pascal GPU. The NVLink point-to-point interconnect’s advantage is enabling data sharing at rates five to 12 times faster than traditional PCI Express Gen 3.0. Currently, the NVLink-based P100 is only available to customers who shell out the $129,000 for NVIDIA’s “deep learning supercomputer,” the DGX-1, but the standalone NVLink-based P100 is expected to hit production availability early 2017.

Intel talks about scalability as being a big difference between a GPU card and Xeon Phi. “With GPU cards, you can only put so many cards in a box,” says Intel’s Barry Davis. “Even with NV-LINK to connect those together, you are still limited in that scale. As you look at the Xeon Phi product line with implementations at thousands of nodes, scalability is a key part of this architecture, and that’s what the market needs today, whether you are talking about machine learning, deep learning or traditional modeling and simulation.”

When it comes to artificial intelligence and deep learning, Intel has published several initial benchmarks claiming performance improvements over GPUs on a number of machine learning workloads.

Intel KNL Phi deep learning-1400x

NVIDIA’s VP, Solutions Architecture and Engineering, Marc Hamilton, said he questions the benchmarks that Intel has released so far, noting that the claims relating to deep learning were done against older versions of GPUs (Kepler) using unoptimized versions of frameworks. [The benchmark breakdown was unavailable on Intel’s site as of press time.] Hamilton also said that the “Knights Landing” does not have the strong node capability of the GPU. NVIDIA GPUs currently scale to 8-way configurations, but the OS will support 16 (recall the K80 has two physical GPUs inside it and the OS will support 8 of these).

There’s also a performance difference between the second-generation Phi and the newest Tesla GPUs. The top bin Knights Landing Phi CPU delivers 3.46 teraflops of double-precision floating point performance. The Pascal P100 GPU for NVLink-optimized servers offers 5.3 teraflops of double-precision floating point performance, and the PCIe version supports 4.7 teraflops of double-precision.

One early customer who has already deployed a Knights Landing Phi-based system is the Texas Advanced Computing Center (TACC) at the University of Austin at Texas. TACC got the 508 node system – an interim step between Stampede 1 and Stampede 2 – up and running and benchmarked on LINPACK three days after receiving its racks.

TACC Director Dan Stanzione wryly commented that that is not his preferred timeframe, but the result was a 117th place ranking on the latest TOP500 with a LINPACK of 817.8 teraflops. “Obviously the software came up pretty quickly in order to make that happen,” said Stanzione.

“We finished all of our benchmarking,” he continued, “and we’re putting users on it this week and are running our first tutorial on Sunday here at ISC.” The system employs the top-bin-minus-1 68-core Xeon Phi 7250 processor and the Omni-Path fabric.

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

Graphcore Readies Launch of 16nm Colossus-IPU Chip

July 20, 2017

A second $30 million funding round for U.K. AI chip developer Graphcore sets up the company to go to market with its “intelligent processing unit” (IPU) in 2017 with scale-up production for enterprise datacenters and Read more…

By Tiffany Trader

Fine-Tuning Severe Hail Forecasting with Machine Learning

July 20, 2017

Depending on whether you’ve been caught outside during a severe hail storm, the sight of greenish tinted clouds on the horizon may cause serious knots in the pit of your stomach, or at least give you pause. There’s g Read more…

By Sean Thielen

Trinity Supercomputer’s Haswell and KNL Partitions Are Merged

July 19, 2017

Trinity supercomputer’s two partitions – one based on Intel Xeon Haswell processors and the other on Xeon Phi Knights Landing – have been fully integrated are now available for use on classified work in the Nationa Read more…

By HPCwire Staff

Fujitsu Continues HPC, AI Push

July 19, 2017

Summer is well under way, but the so-called summertime slowdown, linked with hot temperatures and longer vacations, does not seem to have impacted Fujitsu's output. The Japanese multinational has made a raft of HPC and A Read more…

By Tiffany Trader

HPE Extreme Performance Solutions

HPE Servers Deliver High Performance Remote Visualization

Whether generating seismic simulations, locating new productive oil reservoirs, or constructing complex models of the earth’s subsurface, energy, oil, and gas (EO&G) is a highly data-driven industry. Read more…

Researchers Use DNA to Store and Retrieve Digital Movie

July 18, 2017

From abacus to pencil and paper to semiconductor chips, the technology of computing has always been an ever-changing target. The human brain is probably the computer we use most (hopefully) and understand least. This mon Read more…

By John Russell

The Exascale FY18 Budget – The Next Step

July 17, 2017

On July 12, 2017, the U.S. federal budget for its Exascale Computing Initiative (ECI) took its next step forward. On that day, the full Appropriations Committee of the House of Representatives voted to accept the recomme Read more…

By Alex R. Larzelere

Summer Reading: IEEE Spectrum’s Chip Hall of Fame

July 17, 2017

Take a trip down memory lane – the Mostek MK4096 4-kilobit DRAM, for instance. Perhaps processors are more to your liking. Remember the Sh-Boom processor (1988), created by Russell Fish and Chuck Moore, and named after Read more…

By John Russell

Women in HPC Luncheon Shines Light on Female-Friendly Hiring Practices

July 13, 2017

The second annual Women in HPC luncheon was held on June 20, 2017, during the International Supercomputing Conference in Frankfurt, Germany. The luncheon provides participants the opportunity to network with industry lea Read more…

By Tiffany Trader

Graphcore Readies Launch of 16nm Colossus-IPU Chip

July 20, 2017

A second $30 million funding round for U.K. AI chip developer Graphcore sets up the company to go to market with its “intelligent processing unit” (IPU) in Read more…

By Tiffany Trader

Fine-Tuning Severe Hail Forecasting with Machine Learning

July 20, 2017

Depending on whether you’ve been caught outside during a severe hail storm, the sight of greenish tinted clouds on the horizon may cause serious knots in the Read more…

By Sean Thielen

Fujitsu Continues HPC, AI Push

July 19, 2017

Summer is well under way, but the so-called summertime slowdown, linked with hot temperatures and longer vacations, does not seem to have impacted Fujitsu's out Read more…

By Tiffany Trader

Researchers Use DNA to Store and Retrieve Digital Movie

July 18, 2017

From abacus to pencil and paper to semiconductor chips, the technology of computing has always been an ever-changing target. The human brain is probably the com Read more…

By John Russell

The Exascale FY18 Budget – The Next Step

July 17, 2017

On July 12, 2017, the U.S. federal budget for its Exascale Computing Initiative (ECI) took its next step forward. On that day, the full Appropriations Committee Read more…

By Alex R. Larzelere

Women in HPC Luncheon Shines Light on Female-Friendly Hiring Practices

July 13, 2017

The second annual Women in HPC luncheon was held on June 20, 2017, during the International Supercomputing Conference in Frankfurt, Germany. The luncheon provid Read more…

By Tiffany Trader

Satellite Advances, NSF Computation Power Rapid Mapping of Earth’s Surface

July 13, 2017

New satellite technologies have completely changed the game in mapping and geographical data gathering, reducing costs and placing a new emphasis on time series Read more…

By Ken Chiacchia and Tiffany Jolley

Intel Skylake: Xeon Goes from Chip to Platform

July 13, 2017

With yesterday’s New York unveiling of the new “Skylake” Xeon Scalable processors, Intel made multiple runs at multiple competitive threats and strategic Read more…

By Doug Black

Google Pulls Back the Covers on Its First Machine Learning Chip

April 6, 2017

This week Google released a report detailing the design and performance characteristics of the Tensor Processing Unit (TPU), its custom ASIC for the inference Read more…

By Tiffany Trader

Nvidia Responds to Google TPU Benchmarking

April 10, 2017

Nvidia highlights strengths of its newest GPU silicon in response to Google's report on the performance and energy advantages of its custom tensor processor. Read more…

By Tiffany Trader

Quantum Bits: D-Wave and VW; Google Quantum Lab; IBM Expands Access

March 21, 2017

For a technology that’s usually characterized as far off and in a distant galaxy, quantum computing has been steadily picking up steam. Just how close real-wo Read more…

By John Russell

HPC Compiler Company PathScale Seeks Life Raft

March 23, 2017

HPCwire has learned that HPC compiler company PathScale has fallen on difficult times and is asking the community for help or actively seeking a buyer for its a Read more…

By Tiffany Trader

Trump Budget Targets NIH, DOE, and EPA; No Mention of NSF

March 16, 2017

President Trump’s proposed U.S. fiscal 2018 budget issued today sharply cuts science spending while bolstering military spending as he promised during the cam Read more…

By John Russell

CPU-based Visualization Positions for Exascale Supercomputing

March 16, 2017

In this contributed perspective piece, Intel’s Jim Jeffers makes the case that CPU-based visualization is now widely adopted and as such is no longer a contrarian view, but is rather an exascale requirement. Read more…

By Jim Jeffers, Principal Engineer and Engineering Leader, Intel

Nvidia’s Mammoth Volta GPU Aims High for AI, HPC

May 10, 2017

At Nvidia's GPU Technology Conference (GTC17) in San Jose, Calif., this morning, CEO Jensen Huang announced the company's much-anticipated Volta architecture a Read more…

By Tiffany Trader

Facebook Open Sources Caffe2; Nvidia, Intel Rush to Optimize

April 18, 2017

From its F8 developer conference in San Jose, Calif., today, Facebook announced Caffe2, a new open-source, cross-platform framework for deep learning. Caffe2 is the successor to Caffe, the deep learning framework developed by Berkeley AI Research and community contributors. Read more…

By Tiffany Trader

Leading Solution Providers

How ‘Knights Mill’ Gets Its Deep Learning Flops

June 22, 2017

Intel, the subject of much speculation regarding the delayed, rewritten or potentially canceled “Aurora” contract (the Argonne Lab part of the CORAL “ Read more…

By Tiffany Trader

Reinders: “AVX-512 May Be a Hidden Gem” in Intel Xeon Scalable Processors

June 29, 2017

Imagine if we could use vector processing on something other than just floating point problems.  Today, GPUs and CPUs work tirelessly to accelerate algorithms Read more…

By James Reinders

MIT Mathematician Spins Up 220,000-Core Google Compute Cluster

April 21, 2017

On Thursday, Google announced that MIT math professor and computational number theorist Andrew V. Sutherland had set a record for the largest Google Compute Engine (GCE) job. Sutherland ran the massive mathematics workload on 220,000 GCE cores using preemptible virtual machine instances. Read more…

By Tiffany Trader

Russian Researchers Claim First Quantum-Safe Blockchain

May 25, 2017

The Russian Quantum Center today announced it has overcome the threat of quantum cryptography by creating the first quantum-safe blockchain, securing cryptocurrencies like Bitcoin, along with classified government communications and other sensitive digital transfers. Read more…

By Doug Black

Google Debuts TPU v2 and will Add to Google Cloud

May 25, 2017

Not long after stirring attention in the deep learning/AI community by revealing the details of its Tensor Processing Unit (TPU), Google last week announced the Read more…

By John Russell

Groq This: New AI Chips to Give GPUs a Run for Deep Learning Money

April 24, 2017

CPUs and GPUs, move over. Thanks to recent revelations surrounding Google’s new Tensor Processing Unit (TPU), the computing world appears to be on the cusp of Read more…

By Alex Woodie

Six Exascale PathForward Vendors Selected; DoE Providing $258M

June 15, 2017

The much-anticipated PathForward awards for hardware R&D in support of the Exascale Computing Project were announced today with six vendors selected – AMD Read more…

By John Russell

Top500 Results: Latest List Trends and What’s in Store

June 19, 2017

Greetings from Frankfurt and the 2017 International Supercomputing Conference where the latest Top500 list has just been revealed. Although there were no major Read more…

By Tiffany Trader

  • arrow
  • Click Here for More Headlines
  • arrow
Share This