Intel Launches ‘Knights Landing’ Phi Family for HPC, Machine Learning

By Tiffany Trader

June 21, 2016

From ISC 2016 in Frankfurt, Germany, this week, Intel Corp. launched the second-generation Xeon Phi product family, formerly code-named Knights Landing, aimed at HPC and machine learning workloads. The company had been shipping “Knights Landing” silicon to early customers for the last six months and was waiting to ramp up production before making the product generally available.

The window also gave OEMs time to complete their readiness, said Intel’s Charlie Wuischpard, vice president of the Data Center Group and general manager of High Performance Computing Platform Group, in a media pre-briefing. Those OEMs include the usual names: Cray, HPE, Lenovo, Dell and others.

The most distinguishing feature of the chip is that it’s a bootable host CPU — unlike its predecessor “Knights Corner,” which is a coprocessor that connects over PCIe. “We’re not just a specialized programming model,” said Intel’s General Manager, HPC Compute and Networking, Barry Davis in a hand-on technical demo held at ISC. “We’re the full IA programming model. There’s no PCIe bottleneck; there’s a limitation in the data that you can send back and forth from the host CPU to the accelerator or coprocessor and we removed that bottleneck.”

The “Knights Landing” Phi will be the first chip to offer an integrated fabric, Intel’s Omni-Path Architecture (OPA), in the package. “Knights Landing” also puts integrated on-package memory in a processor, which benefits memory bandwidth and overall application performance. A six-channel memory controller supports up to 384 GB of DDR4-2400 memory (~90GB/s sustained bandwidth). There are 36 PCI Express 3.0 lanes for connecting to PCIe coprocessors, PCIe SSDs or discrete graphics cards.

The second-generation Phi is based on an Intel Atom core (based on the Silvermont microarchitecture) with many HPC enhancements. The MIC (Many Integrated Cores) design fits 8 billion transistors on a die, using 14 nm process technology. The new Phi family introduces the AVX-512 instruction set, which will be available on future Xeon processors. Both the Phi and the Xeon are binary compatible and a benefit of this is that the optimizations that apply to one platform typically carry to the other, notes Intel.

Intel emphasizes that the Phi is designed to run any workload, any IA code. “There are workloads out there that are single thread that maybe benefit from higher frequency and fewer cores and of course you would run those on a Xeon but it doesn’t mean those applications won’t still run on a Xeon Phi,” said Wuischpard. “Some of our early customers are implementing an entire supercomputing cluster with Xeon Phi. Others are doing a mix of Xeon and Xeon Phi and there are a lot of configurations that are possible within a given system deployment.”

As previously announced, the Phi product family comes in three variants: a PCIe coprocessor form factor; a stand-alone CPU; and a stand-alone CPU with integrated Omni-Path fabric technology. The SKU stack that Intel is launching includes four parts with different core counts, frequencies, TDPs and price points.

There are three parts shipping now: the 68-core 7250 (1.4 Ghz), the 64-core 7230 (1.3 Ghz) and the 64-core 7210 (1.3 Ghz). The TDP on all of these is 215 watts. The top-bin part – the Xeon Phi 7290 – is the promised 72-core version. The $6,250 SKU runs at 1.5 Ghz and consumes 245 watts of power; it will not be available until September. Integrated fabric versions of all four parts will not be available until October. Powering the fabric will add another 15 watts to the TDP envelope. The coprocessor card will be available in the second half the year, according to Intel.

Intel KNL Phi SKU list

“You can think of it as the 7200-series Xeon processor,” said Wuischpard, “You’ll see that all of the memory is 16 GBs across the board. We had originally talked about having a richer matrix of SKUs that ranged from no in-package memory to 16 GB of memory and then across these ranges of performance and it just looked too busy and too complex, and in the end everyone wants that in-package memory so we decided to shrink the SKU stack and make it easier to understand. And it does make it easier from a manufacturing perspective.”

The Xeon 7290 is a premium product with a premium price. This is by design since it’s relatively low-yielding, according to Intel. “Most of our early customers and this includes the large research labs and institutions have really focused on the 7230 and the 7250 to get the best price/performance. And we expect the 7210 will be the more general purpose high-running part,” said Wuishpard, adding that it offers 85-90 percent of the performance at less than half the price of the top-end part.

The self-hosted Phi processor competes directly with Tesla GPUs from Nvidia with both products targeting HPC and machine learning and visualization. At its GTC16 event, NVIDIA announced the NVLink-based Pascal GPU. The NVLink point-to-point interconnect’s advantage is enabling data sharing at rates five to 12 times faster than traditional PCI Express Gen 3.0. Currently, the NVLink-based P100 is only available to customers who shell out the $129,000 for NVIDIA’s “deep learning supercomputer,” the DGX-1, but the standalone NVLink-based P100 is expected to hit production availability early 2017.

Intel talks about scalability as being a big difference between a GPU card and Xeon Phi. “With GPU cards, you can only put so many cards in a box,” says Intel’s Barry Davis. “Even with NV-LINK to connect those together, you are still limited in that scale. As you look at the Xeon Phi product line with implementations at thousands of nodes, scalability is a key part of this architecture, and that’s what the market needs today, whether you are talking about machine learning, deep learning or traditional modeling and simulation.”

When it comes to artificial intelligence and deep learning, Intel has published several initial benchmarks claiming performance improvements over GPUs on a number of machine learning workloads.

Intel KNL Phi deep learning-1400x

NVIDIA’s VP, Solutions Architecture and Engineering, Marc Hamilton, said he questions the benchmarks that Intel has released so far, noting that the claims relating to deep learning were done against older versions of GPUs (Kepler) using unoptimized versions of frameworks. [The benchmark breakdown was unavailable on Intel’s site as of press time.] Hamilton also said that the “Knights Landing” does not have the strong node capability of the GPU. NVIDIA GPUs currently scale to 8-way configurations, but the OS will support 16 (recall the K80 has two physical GPUs inside it and the OS will support 8 of these).

There’s also a performance difference between the second-generation Phi and the newest Tesla GPUs. The top bin Knights Landing Phi CPU delivers 3.46 teraflops of double-precision floating point performance. The Pascal P100 GPU for NVLink-optimized servers offers 5.3 teraflops of double-precision floating point performance, and the PCIe version supports 4.7 teraflops of double-precision.

One early customer who has already deployed a Knights Landing Phi-based system is the Texas Advanced Computing Center (TACC) at the University of Austin at Texas. TACC got the 508 node system – an interim step between Stampede 1 and Stampede 2 – up and running and benchmarked on LINPACK three days after receiving its racks.

TACC Director Dan Stanzione wryly commented that that is not his preferred timeframe, but the result was a 117th place ranking on the latest TOP500 with a LINPACK of 817.8 teraflops. “Obviously the software came up pretty quickly in order to make that happen,” said Stanzione.

“We finished all of our benchmarking,” he continued, “and we’re putting users on it this week and are running our first tutorial on Sunday here at ISC.” The system employs the top-bin-minus-1 68-core Xeon Phi 7250 processor and the Omni-Path fabric.

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

UCSD, AIST Forge Tighter Alliance with AI-Focused MOU

January 18, 2018

The rich history of collaboration between UC San Diego and AIST in Japan is getting richer. The organizations entered into a five-year memorandum of understanding on January 10. The MOU represents the continuation of a 1 Read more…

By Tiffany Trader

New Blueprint for Converging HPC, Big Data

January 18, 2018

After five annual workshops on Big Data and Extreme-Scale Computing (BDEC), a group of international HPC heavyweights including Jack Dongarra (University of Tennessee), Satoshi Matsuoka (Tokyo Institute of Technology), Read more…

By John Russell

Researchers Measure Impact of ‘Meltdown’ and ‘Spectre’ Patches on HPC Workloads

January 17, 2018

Computer scientists from the Center for Computational Research, State University of New York (SUNY), University at Buffalo have examined the effect of Meltdown and Spectre security updates on the performance of popular H Read more…

By Tiffany Trader

HPE Extreme Performance Solutions

HPE and NREL Take Steps to Create a Sustainable, Energy-Efficient Data Center with an H2 Fuel Cell

As enterprises attempt to manage rising volumes of data, unplanned data center outages are becoming more common and more expensive. As the cost of downtime rises, enterprises lose out on productivity and valuable competitive advantage without access to their critical data. Read more…

Fostering Lustre Advancement Through Development and Contributions

January 17, 2018

Six months after organizational changes at Intel's High Performance Data (HPDD) division, most in the Lustre community have shed any initial apprehension around the potential changes that could affect or disrupt Lustre Read more…

By Carlos Aoki Thomaz

UCSD, AIST Forge Tighter Alliance with AI-Focused MOU

January 18, 2018

The rich history of collaboration between UC San Diego and AIST in Japan is getting richer. The organizations entered into a five-year memorandum of understandi Read more…

By Tiffany Trader

New Blueprint for Converging HPC, Big Data

January 18, 2018

After five annual workshops on Big Data and Extreme-Scale Computing (BDEC), a group of international HPC heavyweights including Jack Dongarra (University of Te Read more…

By John Russell

Researchers Measure Impact of ‘Meltdown’ and ‘Spectre’ Patches on HPC Workloads

January 17, 2018

Computer scientists from the Center for Computational Research, State University of New York (SUNY), University at Buffalo have examined the effect of Meltdown Read more…

By Tiffany Trader

Fostering Lustre Advancement Through Development and Contributions

January 17, 2018

Six months after organizational changes at Intel's High Performance Data (HPDD) division, most in the Lustre community have shed any initial apprehension aroun Read more…

By Carlos Aoki Thomaz

When the Chips Are Down

January 11, 2018

In the last article, "The High Stakes Semiconductor Game that Drives HPC Diversity," I alluded to the challenges facing the semiconductor industry and how that may impact the evolution of HPC systems over the next few years. I thought I’d lift the covers a little and look at some of the commercial challenges that impact the component technology we use in HPC. Read more…

By Dairsie Latimer

How Meltdown and Spectre Patches Will Affect HPC Workloads

January 10, 2018

There have been claims that the fixes for the Meltdown and Spectre security vulnerabilities, named the KPTI (aka KAISER) patches, are going to affect applicatio Read more…

By Rosemary Francis

Momentum Builds for US Exascale

January 9, 2018

2018 looks to be a great year for the U.S. exascale program. The last several months of 2017 revealed a number of important developments that help put the U.S. Read more…

By Alex R. Larzelere

ANL’s Rick Stevens on CANDLE, ARM, Quantum, and More

January 8, 2018

Late last year HPCwire caught up with Rick Stevens, associate laboratory director for computing, environment and life Sciences at Argonne National Laboratory, f Read more…

By John Russell

Inventor Claims to Have Solved Floating Point Error Problem

January 17, 2018

"The decades-old floating point error problem has been solved," proclaims a press release from inventor Alan Jorgensen. The computer scientist has filed for and Read more…

By Tiffany Trader

US Coalesces Plans for First Exascale Supercomputer: Aurora in 2021

September 27, 2017

At the Advanced Scientific Computing Advisory Committee (ASCAC) meeting, in Arlington, Va., yesterday (Sept. 26), it was revealed that the "Aurora" supercompute Read more…

By Tiffany Trader

Japan Unveils Quantum Neural Network

November 22, 2017

The U.S. and China are leading the race toward productive quantum computing, but it's early enough that ultimate leadership is still something of an open questi Read more…

By Tiffany Trader

AMD Showcases Growing Portfolio of EPYC and Radeon-based Systems at SC17

November 13, 2017

AMD’s charge back into HPC and the datacenter is on full display at SC17. Having launched the EPYC processor line in June along with its MI25 GPU the focus he Read more…

By John Russell

Nvidia Responds to Google TPU Benchmarking

April 10, 2017

Nvidia highlights strengths of its newest GPU silicon in response to Google's report on the performance and energy advantages of its custom tensor processor. Read more…

By Tiffany Trader

IBM Begins Power9 Rollout with Backing from DOE, Google

December 6, 2017

After over a year of buildup, IBM is unveiling its first Power9 system based on the same architecture as the Department of Energy CORAL supercomputers, Summit a Read more…

By Tiffany Trader

Fast Forward: Five HPC Predictions for 2018

December 21, 2017

What’s on your list of high (and low) lights for 2017? Volta 100’s arrival on the heels of the P100? Appearance, albeit late in the year, of IBM’s Power9? Read more…

By John Russell

Chip Flaws ‘Meltdown’ and ‘Spectre’ Loom Large

January 4, 2018

The HPC and wider tech community have been abuzz this week over the discovery of critical design flaws that impact virtually all contemporary microprocessors. T Read more…

By Tiffany Trader

Leading Solution Providers

Perspective: What Really Happened at SC17?

November 22, 2017

SC is over. Now comes the myriad of follow-ups. Inboxes are filled with templated emails from vendors and other exhibitors hoping to win a place in the post-SC thinking of booth visitors. Attendees of tutorials, workshops and other technical sessions will be inundated with requests for feedback. Read more…

By Andrew Jones

Tensors Come of Age: Why the AI Revolution Will Help HPC

November 13, 2017

Thirty years ago, parallel computing was coming of age. A bitter battle began between stalwart vector computing supporters and advocates of various approaches to parallel computing. IBM skeptic Alan Karp, reacting to announcements of nCUBE’s 1024-microprocessor system and Thinking Machines’ 65,536-element array, made a public $100 wager that no one could get a parallel speedup of over 200 on real HPC workloads. Read more…

By John Gustafson & Lenore Mullin

Delays, Smoke, Records & Markets – A Candid Conversation with Cray CEO Peter Ungaro

October 5, 2017

Earlier this month, Tom Tabor, publisher of HPCwire and I had a very personal conversation with Cray CEO Peter Ungaro. Cray has been on something of a Cinderell Read more…

By Tiffany Trader & Tom Tabor

Flipping the Flops and Reading the Top500 Tea Leaves

November 13, 2017

The 50th edition of the Top500 list, the biannual publication of the world’s fastest supercomputers based on public Linpack benchmarking results, was released Read more…

By Tiffany Trader

GlobalFoundries, Ayar Labs Team Up to Commercialize Optical I/O

December 4, 2017

GlobalFoundries (GF) and Ayar Labs, a startup focused on using light, instead of electricity, to transfer data between chips, today announced they've entered in Read more…

By Tiffany Trader

How Meltdown and Spectre Patches Will Affect HPC Workloads

January 10, 2018

There have been claims that the fixes for the Meltdown and Spectre security vulnerabilities, named the KPTI (aka KAISER) patches, are going to affect applicatio Read more…

By Rosemary Francis

HPC Chips – A Veritable Smorgasbord?

October 10, 2017

For the first time since AMD's ill-fated launch of Bulldozer the answer to the question, 'Which CPU will be in my next HPC system?' doesn't have to be 'Whichever variety of Intel Xeon E5 they are selling when we procure'. Read more…

By Dairsie Latimer

Nvidia, Partners Announce Several V100 Servers

September 27, 2017

Here come the Volta 100-based servers. Nvidia today announced an impressive line-up of servers from major partners – Dell EMC, Hewlett Packard Enterprise, IBM Read more…

By John Russell

  • arrow
  • Click Here for More Headlines
  • arrow
Share This