While several product and technology announcements were forthcoming from Intel at ISC, first and foremost was the visionary keynote—AI, and more, on IA—from Rajeeb Hazra, VP of Intel’s Data Center Group. In it he describes how accurately supporting just 20,000 autonomous cars would require an ExaFLOP of sustained compute. It would involve a network of millions of sensors inside and outside the cars and their interpretation, plus the deep learning needed to constantly stay aware of the world around them and the drivers inside them, and repeatedly pass new models to the cars. Then he moves on to explain some of the other key drivers of Exascale that will deliver real economic, social and commercial benefits:
- Natural language processing where computers would speak our lingua franca and not vice-versa,
- Image recognition and the massive scale advancement in deep learning and associated computing power to make it real, and
- Artificial intelligence where computers would have the algorithmic clarity and compute power to navigate through the choices of multi-player games, for example.
He also provided insights on Intel’s roadmaps, motivations, technologies, and product announcements. The first announcement was the much-anticipated introduction of the Intel® Xeon Phi processor (formerly code named Knight’s Landing)—Intel’s first bootable host processor for highly parallel computing workloads. He also introduced Intel® HPC Orchestrator, the Intel-supported OpenHPC system software stack, and provided new details about Intel® Scalable System Framework configurations including a new reference architecture specification and reference designs.
In speaking about the Intel Xeon Phi processor, Hazra said, “We have proven the performance benefits of such an architecture that accelerates faster than an accelerator without requiring such a tremendous disruption to the programming model.”1
Five live booth demos showcased interactive visualization demonstrations running on an Intel Scalable System Framework cluster using the new Intel Xeon Phi processors 7210 with 64 cores each booted in self-hosted mode. The demos included:
- École Polytechnique Fédérale de Lausanne (EPFL) showed how computer and biological scientists take neural morphologies and reconstruct a piece of neocortex brain tissue, representing the cell structure using parametric geometry. The demo highlighted how multi-core based visualization is now a viable and performant path in lieu of GPU based visualization.
- Kyoto University demonstrated how dual-socket Intel® Xeon E5-2699v3 (Haswell architecture) server delivers better performance than an NVIDIA K40 GPU using 16-bit arithmetic (which doubles GPU performance) when training deep learning neural networks for computational drug discovery using the Theano framework.
- Researchers from the Stephen Hawking Center for Theoretical Cosmology provided a simulation that visualized two black holes colliding and generating gravitation waves in super real time. The demo features 3D volume rendering using Adaptive Mesh Refinement (AMR) at the full resolution of the input data.
To help developers get off to an early start with parallel programming on the Intel Xeon Phi processor, former director and chief evangelist for Intel® Software, James Reinders, plus Intel colleagues Jim Jeffers and Avinash Sodani, released their new book at ISC called Intel® Xeon Phi Processor High Performance Programming: Knights Landing Edition.
In speaking about the newly announced Intel Xeon Phi processors, which could be seen in numerous demos throughout ISC, Reinders explained, “Knights Landing is a full-fledged, highly scalable Intel processor. The vision for this new device was to create a processor that could reach unprecedented levels of performance and parallelism, without giving up programmability. In other words, you can use the same parallel programming models, the same tools, the same binaries that are in common use today by other members of the Intel® Xeon® processor family.”
1 https://newsroom.intel.com/newsroom/wp-content/uploads/sites/11/2016/06/Intel-ISC16-press-deck-x.pdf