ISC Workshop Tackles the Co-development Challenge

By John Russell

July 12, 2016

The long percolating discussion over ‘co-development’ and how best it should be undertaken has gained new urgency in the race towards exascale computing. At a workshop held at ISC2016 last month – Form Follows Function: Do algorithms and applications challenge or drag behind the hardware evolution? – several distinguished panelists offered varying viewpoints. Yesterday, session organizer Tobias Weinzierl posted a summary synopsis of the workshop discussion on arXiv.org.

Weinzierl (Durham University) and co-organizer Michael Bader (Technische Universität München) are active participants in the ExaHyPE project (An Exascale Hyperbolic PDE (partial differential equation) Engine [1], funded by EU’s Horizon 2020 program). ExaHyPE focuses on the development of new mathematical and algorithmic approaches to exascale systems – initially for simulations in geophysics and astrophysics. During the four-year project, researchers from institutions in Germany, Italy, United Kingdom, and Russia will develop novel software for performing simulations on exascale supercomputers.

Seven European supercomputing projects were invited to the workshop to “share their views on the interplay of hardware and software evolution,” giving the workshop a distinctly European flavor. Among the speakers and organizations represented were:

DruckWeinzierl wrote that technology roadmaps are dominated by predictions on hardware. “At the same time, hardware-software co-design is a frequently cited phrase. It suggests that software development can have an impact on the hardware evolution. It can actively shape. The workshop members clarified in their talks to which degree this assumption holds in the context of their projects, what the interaction of hardware and software development looks like and weather the interplay is positive and should be fostered or manipulative and slows down scientific progress?”

He also noted pointedly, “As the workshop invited European projects, this document has a strong European flavour. This is important to keep in mind given that we discuss aspects of co-design—in a business that is dominated by US vendors. Furthermore, almost all invited projects emphasize aspects of simulation software development and integration into classic simulation workflows. We do not really discuss co-design in a co-design setting: all statements on co-design are made from a scientific computing’s software point of view. Last but not least, some statements are on purpose pointed.”

Here’s an excerpt from Weinzierl’s summary report (the report itself is brief and best read in full (link below)):

Running in circles: Does co-design happen (outside co-design projects)?

  • “Any discussion on hardware-software/software-hardware influence has to start from a clarification whether such a cycle does exist and what it looks like. The workshop opened with a presentation by Jack Dongarra who sketched such a cycle. LINPACK [3] with its emphasis on vectors fits to a particular type of machine. It was written at a time when it had been important to tackle the thorny fact that floating point operations are expensive. LAPACK [4] anticipates the advent of caches where keeping the floating point units busy gains importance. ScaLAPACK’s [5] design was kicked off by multi-node machines with MPI, while the dusk of BSP triggers the development of Magma [6] and Plasma [7]. The latter are subject of study in the NLAFET project [8]. Mark Parsons gave another example as he outlined how the availability of 3D XPoint non-volatile memory [9] laid the foundations of the NEXTGenIO project [10] 2 studying how to use additional memory layers between main memory and hard disk.
  • Jack Dongarra
    Jack Dongarra

    “While it is easy to follow how hardware development triggers new algorithmic work—our own ExaHyPE [1] project hypothesising that hardware will suffer from severe performance fluctuations is an example for this, too—Jack pointed out that the (Top 500) benchmarks in turn grew downstreamingly into a directing role for the hardware evolution, as they make vendors tune their machines towards these benchmarks; though this has never been the intention behind them in the first place as he emphasised. Other examples for the influence back are the increasing IO demands of today’s software as sketched before, or GPGPU modifications as Peter Messmer illustrated at hands of the Escape project [11]: atomics and double precision would not have made it into GPUs that fast if there had not been a demand of these features from the scientific computing side. After all, machines are procured because of scientific software needs. So while we see software written from scratch around every ten years because of transformative hardware developments, in-between software continuously influences the hardware evolution; mainly by acting as benchmarks or as they escalate bottlenecks.”

Weinzierl wrote, “Most workshop participants were skeptical whether the cycle of influence is a good one the way we experience it right now: It orbits around weaknesses and demands. It is backward looking. Mark articulated that he is worried that the evolution even does not take the well-known Amdahl numbers into account [13]: “I believe strongly in co-design but it happens extremely rarely”.

As noted early, Weinzierl’s summary report is short and best read in full. Here’s a link to the report: http://arxiv.org/pdf/1607.02835v1.pdf

References

[1] www.exahype.eu
[2] www.exascale.org/mediawiki/images/2/20/IESP-roadmap.pdf
[3] www.netlib.org/linpack
[4] www.netlib.org/lapack
[5] www.netlib.org/scalapack
[6] icl.cs.utk.edu/magma
[7] icl.cs.utk.edu/plasma
[8] www.nlafet.eu
[9] www.micron.com/about/emerging-technologies/3d-xpoint-technology
[10] www.nextgenio.eu
[11] www.hpc-escape.eu
[12] www.isc-hpc.com
[13] www.microsoft.com/en-us/research/publication/rules-of-thumb-in-data-engineering
[14] exaflow-project.eu

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

The Case for an Edge-Driven Future for Supercomputing

September 24, 2021

“Exascale only becomes valuable when it’s creating and using data that we care about,” said Pete Beckman, co-director of the Northwestern-Argonne Institute of Science and Engineering (NAISE), at the most recent HPC Read more…

Three Universities Team for NSF-Funded ‘ACES’ Reconfigurable Supercomputer Prototype

September 23, 2021

As Moore’s law slows, HPC developers are increasingly looking for speed gains in specialized code and specialized hardware – but this specialization, in turn, can make testing and deploying code trickier than ever. Now, researchers from Texas A&M University, the University of Illinois at Urbana... Read more…

Qubit Stream: Monte Carlo Advance, Infosys Joins the Fray, D-Wave Meeting Plans, and More

September 23, 2021

It seems the stream of quantum computing reports never ceases. This week – IonQ and Goldman Sachs tackle Monte Carlo on quantum hardware, Cambridge Quantum pushes chemistry calculations forward, D-Wave prepares for its Read more…

Asetek Announces It Is Exiting HPC to Protect Future Profitability

September 22, 2021

Liquid cooling specialist Asetek, well-known in HPC circles for its direct-to-chip cooling technology that is inside some of the fastest supercomputers in the world, announced today that it is exiting the HPC space amid multiple supply chain issues related to the pandemic. Although pandemic supply chain... Read more…

TACC Supercomputer Delves Into Protein Interactions

September 22, 2021

Adenosine triphosphate (ATP) is a compound used to funnel energy from mitochondria to other parts of the cell, enabling energy-driven functions like muscle contractions. For ATP to flow, though, the interaction between the hexokinase-II (HKII) enzyme and the proteins found in a specific channel on the mitochondria’s outer membrane. Now, simulations conducted on supercomputers at the Texas Advanced Computing Center (TACC) have simulated... Read more…

AWS Solution Channel

Introducing AWS ParallelCluster 3

Running HPC workloads, like computational fluid dynamics (CFD), molecular dynamics, or weather forecasting typically involves a lot of moving parts. You need a hundreds or thousands of compute cores, a job scheduler for keeping them fed, a shared file system that’s tuned for throughput or IOPS (or both), loads of libraries, a fast network, and a head node to make sense of all this. Read more…

The Latest MLPerf Inference Results: Nvidia GPUs Hold Sway but Here Come CPUs and Intel

September 22, 2021

The latest round of MLPerf inference benchmark (v 1.1) results was released today and Nvidia again dominated, sweeping the top spots in the closed (apples-to-apples) datacenter and edge categories. Perhaps more interesti Read more…

The Case for an Edge-Driven Future for Supercomputing

September 24, 2021

“Exascale only becomes valuable when it’s creating and using data that we care about,” said Pete Beckman, co-director of the Northwestern-Argonne Institut Read more…

Three Universities Team for NSF-Funded ‘ACES’ Reconfigurable Supercomputer Prototype

September 23, 2021

As Moore’s law slows, HPC developers are increasingly looking for speed gains in specialized code and specialized hardware – but this specialization, in turn, can make testing and deploying code trickier than ever. Now, researchers from Texas A&M University, the University of Illinois at Urbana... Read more…

Qubit Stream: Monte Carlo Advance, Infosys Joins the Fray, D-Wave Meeting Plans, and More

September 23, 2021

It seems the stream of quantum computing reports never ceases. This week – IonQ and Goldman Sachs tackle Monte Carlo on quantum hardware, Cambridge Quantum pu Read more…

Asetek Announces It Is Exiting HPC to Protect Future Profitability

September 22, 2021

Liquid cooling specialist Asetek, well-known in HPC circles for its direct-to-chip cooling technology that is inside some of the fastest supercomputers in the world, announced today that it is exiting the HPC space amid multiple supply chain issues related to the pandemic. Although pandemic supply chain... Read more…

TACC Supercomputer Delves Into Protein Interactions

September 22, 2021

Adenosine triphosphate (ATP) is a compound used to funnel energy from mitochondria to other parts of the cell, enabling energy-driven functions like muscle contractions. For ATP to flow, though, the interaction between the hexokinase-II (HKII) enzyme and the proteins found in a specific channel on the mitochondria’s outer membrane. Now, simulations conducted on supercomputers at the Texas Advanced Computing Center (TACC) have simulated... Read more…

The Latest MLPerf Inference Results: Nvidia GPUs Hold Sway but Here Come CPUs and Intel

September 22, 2021

The latest round of MLPerf inference benchmark (v 1.1) results was released today and Nvidia again dominated, sweeping the top spots in the closed (apples-to-ap Read more…

Why HPC Storage Matters More Now Than Ever: Analyst Q&A

September 17, 2021

With soaring data volumes and insatiable computing driving nearly every facet of economic, social and scientific progress, data storage is seizing the spotlight. Hyperion Research analyst and noted storage expert Mark Nossokoff looks at key storage trends in the context of the evolving HPC (and AI) landscape... Read more…

GigaIO Gets $14.7M in Series B Funding to Expand Its Composable Fabric Technology to Customers

September 16, 2021

Just before the COVID-19 pandemic began in March 2020, GigaIO introduced its Universal Composable Fabric technology, which allows enterprises to bring together Read more…

Ahead of ‘Dojo,’ Tesla Reveals Its Massive Precursor Supercomputer

June 22, 2021

In spring 2019, Tesla made cryptic reference to a project called Dojo, a “super-powerful training computer” for video data processing. Then, in summer 2020, Tesla CEO Elon Musk tweeted: “Tesla is developing a [neural network] training computer called Dojo to process truly vast amounts of video data. It’s a beast! … A truly useful exaflop at de facto FP32.” Read more…

Enter Dojo: Tesla Reveals Design for Modular Supercomputer & D1 Chip

August 20, 2021

Two months ago, Tesla revealed a massive GPU cluster that it said was “roughly the number five supercomputer in the world,” and which was just a precursor to Tesla’s real supercomputing moonshot: the long-rumored, little-detailed Dojo system. “We’ve been scaling our neural network training compute dramatically over the last few years,” said Milan Kovac, Tesla’s director of autopilot engineering. Read more…

Esperanto, Silicon in Hand, Champions the Efficiency of Its 1,092-Core RISC-V Chip

August 27, 2021

Esperanto Technologies made waves last December when it announced ET-SoC-1, a new RISC-V-based chip aimed at machine learning that packed nearly 1,100 cores onto a package small enough to fit six times over on a single PCIe card. Now, Esperanto is back, silicon in-hand and taking aim... Read more…

CentOS Replacement Rocky Linux Is Now in GA and Under Independent Control

June 21, 2021

The Rocky Enterprise Software Foundation (RESF) is announcing the general availability of Rocky Linux, release 8.4, designed as a drop-in replacement for the soon-to-be discontinued CentOS. The GA release is launching six-and-a-half months after Red Hat deprecated its support for the widely popular, free CentOS server operating system. The Rocky Linux development effort... Read more…

Intel Completes LLVM Adoption; Will End Updates to Classic C/C++ Compilers in Future

August 10, 2021

Intel reported in a blog this week that its adoption of the open source LLVM architecture for Intel’s C/C++ compiler is complete. The transition is part of In Read more…

Hot Chips: Here Come the DPUs and IPUs from Arm, Nvidia and Intel

August 25, 2021

The emergence of data processing units (DPU) and infrastructure processing units (IPU) as potentially important pieces in cloud and datacenter architectures was Read more…

AMD-Xilinx Deal Gains UK, EU Approvals — China’s Decision Still Pending

July 1, 2021

AMD’s planned acquisition of FPGA maker Xilinx is now in the hands of Chinese regulators after needed antitrust approvals for the $35 billion deal were receiv Read more…

Google Launches TPU v4 AI Chips

May 20, 2021

Google CEO Sundar Pichai spoke for only one minute and 42 seconds about the company’s latest TPU v4 Tensor Processing Units during his keynote at the Google I Read more…

Leading Solution Providers

Contributors

HPE Wins $2B GreenLake HPC-as-a-Service Deal with NSA

September 1, 2021

In the heated, oft-contentious, government IT space, HPE has won a massive $2 billion contract to provide HPC and AI services to the United States’ National Security Agency (NSA). Following on the heels of the now-canceled $10 billion JEDI contract (reissued as JWCC) and a $10 billion... Read more…

10nm, 7nm, 5nm…. Should the Chip Nanometer Metric Be Replaced?

June 1, 2020

The biggest cool factor in server chips is the nanometer. AMD beating Intel to a CPU built on a 7nm process node* – with 5nm and 3nm on the way – has been i Read more…

Julia Update: Adoption Keeps Climbing; Is It a Python Challenger?

January 13, 2021

The rapid adoption of Julia, the open source, high level programing language with roots at MIT, shows no sign of slowing according to data from Julialang.org. I Read more…

Quantum Roundup: IBM, Rigetti, Phasecraft, Oxford QC, China, and More

July 13, 2021

IBM yesterday announced a proof for a quantum ML algorithm. A week ago, it unveiled a new topology for its quantum processors. Last Friday, the Technical Univer Read more…

Intel Launches 10nm ‘Ice Lake’ Datacenter CPU with Up to 40 Cores

April 6, 2021

The wait is over. Today Intel officially launched its 10nm datacenter CPU, the third-generation Intel Xeon Scalable processor, codenamed Ice Lake. With up to 40 Read more…

Frontier to Meet 20MW Exascale Power Target Set by DARPA in 2008

July 14, 2021

After more than a decade of planning, the United States’ first exascale computer, Frontier, is set to arrive at Oak Ridge National Laboratory (ORNL) later this year. Crossing this “1,000x” horizon required overcoming four major challenges: power demand, reliability, extreme parallelism and data movement. Read more…

Intel Unveils New Node Names; Sapphire Rapids Is Now an ‘Intel 7’ CPU

July 27, 2021

What's a preeminent chip company to do when its process node technology lags the competition by (roughly) one generation, but outmoded naming conventions make it seem like it's two nodes behind? For Intel, the response was to change how it refers to its nodes with the aim of better reflecting its positioning within the leadership semiconductor manufacturing space. Intel revealed its new node nomenclature, and... Read more…

Latest MLPerf Results: Nvidia Shines but Intel, Graphcore, Google Increase Their Presence

June 30, 2021

While Nvidia (again) dominated the latest round of MLPerf training benchmark results, the range of participants expanded. Notably, Google’s forthcoming TPU v4 Read more…

  • arrow
  • Click Here for More Headlines
  • arrow
HPCwire