Momentum for open source hardware made a significant advance this week with the launch of startup SiFive and its open source chip platforms based on the RISC-V instruction set architecture. The founders of the fabless semiconductor company — Krste Asanovic, Andrew Waterman, and Yunsup Lee — invented the free and open RISC-V ISA at the University of California, Berkeley, six years ago.

The progression of RISC-V and the launch of SiFive opens the door to a new way of chip building that skirts prohibitive licensing costs and lowers the barrier to entry for custom chip design. The traction around RISC-V and other open source hardware efforts like the Facebook-initiated Open Compute Project, and to some extent even the growing diversity in the processor space, which reflects a demand for more openness and choice, may indicate the beginnings of a revolution similar to the one started by Linux on the software side.

Jack Kang, vice president of product and business development, addressed the significance of an open instruction set architecture and this trend toward open hardware.

“The economic demise of Moore’s law can no longer be disputed,” he shared. “The cost per transistor is no longer decreasing. The fixed cost to start a new design continues to rise. Due to these factors, we have seen incredible change in the semiconductor industry. The industry has been set up for the past 30, 40 years based on Moore’s law. How they engineer chips, what products they build, how they work with customers, all of that is based on 30+ years of legacy. Last year, we saw over $100B in mergers & acquisition activity in the semiconductor space, due to these factors and the requirement to look for larger and larger customer volume sockets.”

Designing a custom chip can cost tens and even hundreds of millions of dollars, said SiFive Co-founder Yunsup Lee in an official statement. “It is simply impossible for smaller system designers to get a modern, high-performance chip, much less one customized to their unique requirements.”

SiFive sees custom silicon as an opportunity for the markets that are not being adequately served by the traditional semiconductors. The founders want to democratize access to custom silicon beyond the big players to the inventors, makers, startups, and smallest companies. Included here are fragmented or new markets that do not have the volume or revenue required under the conventional proprietary semiconductor approach, Kang said.

Target markets for SiFive span machine learning, storage and networking as well as the fast-growing IoT market with the launch of two platforms:

The Freedom U500 Series — part of the Freedom Unleashed family — includes a Linux-capable embedded application processor with multicore RISC-V CPUs, running at a speed of 1.6 GHz or higher with support for accelerators and cache coherency. This SoC was manufactured by TSMC on 28nm process and targets the machine learning, storage and networking space. The U500 supports PCIe 3.0, USB 3.0, Gigabit Ethernet, and DDR3/DDR4.

The Freedom E300 Series, the first product in the Freedom Everywhere family, is aimed at the embedded microcontroller, IoT and wearables markets. The 180nm TSMC chip implements small and efficient RISC-V cores with RISC-V compressed instructions, shown to reduce code size by up to 30 percent, according to the company.

In-depth guides for both platforms are available here.

Kang said that he and his colleagues have been witnessing the benefits of the growth of the RISC-V ecosystem. To this point, RISC-V Foundation has more than doubled membership since January. At the last RISC-V workshop in January, there were only 16 member companies, reports Kang, and that roster now includes 40 member companies, including heavyweights Google, Microsoft, IBM, NVIDIA, HP Enterprise, AMD, Qualcomm, Western Digital and Oracle.

SiFive timed its launch to coincide with the 4th RISC-V workshop, happening this week in Boston, where the founders demoed both platforms.

While SiFive is focusing on the embedded and industrial space, the opportunity exists to use RISC-V for other purposes, including server-class silicon. The ISA’s designers sought to ensure that it would support implementation in an ASIC, FPGA or full-custom architecture. Earlier this year at the Stanford HPC Conference, MIT’s Kurt Keville said that RISC-V addresses several of the exascale challenges that were included in the DOE’s oft-cited Exascale report. RISC-V also works well as a teaching tool in academia, said Keville, having a fraction of the instructions of x86 (177 versus roughly 3,000) and about fifth that of ARMv8 (with about 1,000 instructions).

There is even a chapter in the RISC-V ISA manual covering a variant of the RISC-V ISA that supports a flat 128-bit address space, which has promise for future extreme-scale systems.

Here the manual notes:

“At the time of writing, the fastest supercomputer in the world as measured by the Top500 benchmark had over 1 PB of DRAM, and would require over 50 bits of address space if all the DRAM resided in a single address space. Some warehouse-scale computers already contain even larger quantities of DRAM, and new dense solid-state non-volatile memories and fast interconnect technologies might drive a demand for even larger memory spaces. Exascale systems research is targeting 100 PB memory systems, which occupy 57 bits of address space. At historic rates of growth, it is possible that greater than 64 bits of address space might be required before 2030.”

At the time of launch, SiFive has one announced customer, Microsemi Corporation, which is also a partner for its FPGA dev boards. The company’s SoC business unit worked with SiFive to build a complete RISC-V sub-system and tool-chain targeting its low power SmartFusion2 SoC FPGA platform. FPGA Freedom platforms are available now.

“We think the industry needs to change,” Kang reflected. “Open-source hardware has the potential to be the solution this industry needs [and] RISC-V has the benefit of being designed for modern software stacks and modern circuit techniques. It’s simple, modern, and clean.”