The final International Technology Roadmap for Semiconductors (ITRS) is now out. The highly-detailed multi-part report, collaboratively published by a group of international semiconductor experts, offers guidance on the technological challenges and opportunities for the semiconductor industry through 2030. One of the major takeaways is the insistence that Moore’s law will continue for some time even though traditional transistor scaling (through smaller feature sizes) is expected to hit an economic wall in 2021.
In the executive summary, the report takes a hard “long live Moore’s Law” stance, calling out media for getting it wrong: “The question of how long will Moore’s Law last has been posed an infinite number of times since the 80s and every 5-10 years publications claiming the end of Moore’s Law have appeared from the most unthinkable and yet ‘reputedly qualified’ sources. Despite these alarmist publications the trend has continued unabated for the past 50 years by morphing from one scaling method to another, where one method ended the next took over. This concept has completely eluded the comprehension of casual observers that have mistakenly interpreted the end of one scaling method as the end of Moore’s law. As stated before, bipolar transistors were replaced by PMOS that were replaced by NMOS that were also replaced by CMOS. Equivalent Scaling succeeded Geometrical Scaling when this could no longer operate and now 3D Power Scaling is taking off.”
In its strictest sense the observation-turned-prophecy made by Gordon Moore in 1965 specifies that the number of transistors on an integrated circuit will double every 18-24 months, but the “law” is also used as shorthand for faster, cheaper processing power. When it comes to this second interpretation, doubling transistor densities hasn’t resulted in significantly higher performance since the loss of Dennard scaling about a decade ago.
“We’ve been living in this bubble where the computing industry could rely on the device side to do their job, and so the computer industry and the device industry really had this very nice wall between them. That wall really started to crumble in 2005, and since that time we’ve been getting more transistors but they’re really not all that much better,” said Tom Conte, the 2015 president of the IEEE Computer Society and a co-leader of the IEEE Rebooting Computing Initiative, in an interview with IEEE Spectrum.
The ITRS is anticipating that the industry will move away from FinFET to gate-all-around (GAA) and potentially to vertical nanowires in the 2019 timeframe. This will be needed when gate length scaling is constrained by the limits of fin width and contact width, say the authors. Maintaining performance, reliability and other requirements at scale will require material innovations, e.g., “high-k gate dialetrics, metal gate electrodes, elevated source/drain, advanced annealing and doping techniques, low-k materials.”
By 2020, feature sizes will be down to just a few nanometers, at which point, vertical scaling is set to become more economical. The “rather obvious” solution to running out of horizontal space is go vertical, say the authors, noting that the approach is already being demonstrated in the flash memory space.
“Orienting the transistor substrate vertically and then completely surrounding it with a sequence of dielectric and metal layers deposited by means of deposition to fabricate the composite gate structure can more easily [be] accomplished if the transistor is vertically oriented,” states the report. “It is clear that this method reduces the transistor footprint and in conjunction with creating multiple layers of transistors one on top of the other will accelerate the level of transistor density beyond Moore’s Law traditional trends.”
Section 5 of the report focuses on “More Moore” challenges, referring to the need to improve functionalities that do not necessarily scale according to Moore’s law. Even with the benefit of Moore’s scaling, system scaling is limited by power and interconnect bandwidth, for example.
The authors point to three applications that are driving innovations:
+ High-performance computing – targeting more performance (operating frequency) at constant power density (constrained by thermal).
+ Mobile computing – tartgeting more performance (operating frequency) and functionality at constant energy (constrained by battery) and cost.
+ Autonomous sensing & computing (Internet-of-Things: IoT) – targeting reduced leakage & variability.
The section explores the physical, electrical and reliability requirements for logic and memory technologies to sustain PPAC (power, performance, area and cost) scaling. Ideally, node-to-node scaling would achieve gains in line with the following “PPAC” values every 2-3 years:
+ (P)erformance: <30% more maxiumum operating frequency at constant energy
+ (P)ower: >50% less energy per switching at given performance
+ (A)rea: >50% area reduction
+ (C)ost: <25% wafer cost – 35-40% less die cost for scaled die
With the acknowledgement that dimensional scaling is no longer sufficient to sustain higher speed, higher density, lower power and greater functionality, this section of the ITRS report focuses on key challenge areas related to processing modules, tools, material properties and other relevant technologies.
The End of ITRS
The current report, titled ITRS 2.0 2015 Edition, is the last one that will be published. The global roadmap has been updated nearly every year since the first version in 1998. Its predecessor, the National Technology Roadmap for Semiconductors, was started by the US trade group, the Semiconductor Industry Association (SIA), in 1993. SIA’s membership roster includes Intel, AMD, IBM and many other industry heavyweights.
As explanation for the disbanding of ITRS, SIA, a major ITRS sponsor, stated: “Faced with ever-evolving research needs and technology challenges, industry leaders have decided to conclude the ITRS and transition to new ways to advance semiconductor research and bring about the next generation of semiconductor innovations.”
SIA will continue to conduct its own research and will also collaborate with the Semiconductor Research Association. Further, the IEEE, as part of its Rebooting Computing initiative, has started a more general roadmapping project, called the International Roadmap for Devices and Systems or IRDS.