Intel’s Fryman: “It’s not that we love CMOS; it’s the only real choice.”

By John Russell

September 1, 2016

Forget for a moment the prevailing high anxiety over Moore’s law’s fate. In the near-term – which could easily mean a decade – CMOS will remain the only viable, volume technology driving computing. Pursue alternatives? Of course, urged Josh Fryman, principal engineer and engineering manager, Intel. But more can and must be done to advance CMOS-based architecture and Intel, not surprisingly, has a few ideas.

Fryman was one of three speakers scanning the horizon at ISC2016’s Scaling Beyond the End of Moore’s Law session. It was fascinating conversation covering quantum computing, neuromorphic computing, and today’s workhorse, CMOS.

Damian Steiger, a researcher at the Platform for Advanced Scientific Computing and the Institute for Theoretical Physics of ETH Zurich, tackled quantum computing. Figuring out how to actually implement quantum computing and identifying killer quantum applications to attract needed funding formed much of his talk. He had three applications in mind although wasn’t especially optimistic we’ll see useful quantum computers anytime soon with the possible exception of government-funded efforts aimed at decrypting RSA.

Karheinz Meier from the Human Brain Project tackled neuromorphic computing. Here, the near-term future seems brighter. Meier expects the recent availability of three large-scale neuromorphic computing systems for application development to push progress more quickly. (See HPCwire article, Think Fast – Is Neuromorphic Computing Set to Leap Forward?)

It fell to Fryman, the opening speaker, to remind everyone that as promising as many new directional efforts look, it takes years to work out the bugs and turn a new technology into a large-scale manufacturing-friendly process. Interestingly, according to Fryman, advancing CMOS will mostly involve reviving old ideas that were problematic in the past but are unavoidable now. It will also require thinking far more holistically about how hardware and software play together.

Josh Fryman, Intel
Josh Fryman, Intel

“We need to find the Neo of the next generation [computational technology],” agreed Fryman, referring to the protagonist in the film, The Matrix, whose abilities jumped over those around him, “but once you find it, once you work out the techniques, you still have a long haul to make it something we could use, something viable for mass production.

“Until then what are we going to do? The short answer is CMOS is going to continue. It’s not because it is necessarily the best technology, it’s not because we particularly like it and adore it, it’s because we have no choice to keep everything moving forward.”

In setting the context for his talk, Fryman emphasized it’s important to remember that Moore’s law is a business statement not a technology law. That said, Moore’s law has become a surrogate for many things, including the pace of semiconductor technology advance. Its current “difficulties” (Dennard scaling, et al.) have, of course, been widely discussed with Intel holding strong against the growing opinion that Moore’s law’s days are numbered. (See HPCwire article, Moore’s Law – Not Dead – and Intel’s Use of HPC to Keep it Alive)

Fryman noted the classic recipe for engineers to achieve Moore’s law for transistors has been “to scale your dimensions, to scale your supply, and you’re done. You just keep turning the crank on this over and over. The running joke is years ago in the fab we used just a handful of elements in the periodic table. Today we use just about all of the elements except for a handful to get the same job done. [But at the end of the day] it’s still just a recipe.”

From an engineering perspective, what happens when the recipe fails? Fryman briefly reminded the audience that change is hardly new in electronics but that a few common underlying characteristics have been necessary for progress.

“If you look at the evolution of electronics, moving from mechanical to electromechanical, to vacuums tubes, to bipolar, to NMOS, to PMOS, and ultimately CMOS, and now you have this questions about what is coming. If you look at the trend line historically, each of the crossings is defined by having three basic components. You have to have gain; signal to noise control; and scalability, although scalability is really an overused term. What does it really mean? You’re talking about three dimensions: performance, energy, and pricing. These are the three fundamentals for something to actually be a viable technology and it needs to be ‘friendly to high volume manufacturing.’”

Intel KNL Phi die shot
Intel KNL Phi die shot

As there is no obvious technology to replace CMOS now, the focus must be on how to use what we know. This is doable, maintains Fryman, but will require rethinking existing approaches and in some instances re-learning old lessons. He said a trio of strategies will drive advances in underlying CMOS and compute architectures.

  • Remove waste to reclaim efficiency. Die area, for example, has ballooned to accommodate accumulating features such as pipelines, onchip floating point, out-of-order execution, etc. In many cases performance, and in most cases power consumption, have suffered. Review of accumulated features with an eye towards simplification and elimination will play a role.
  • Use known techniques. Over the years, lots of manufacturing and chip design approaches have been tried and tested and well characterized, including their drawbacks, “but people wanted to avoid them because they were considered hard at some level, too hard to program, to hard to use, too hard to design. But when you are running out of other knobs [to adjust] these are not as hard anymore.”
  • Multidisciplinary solutions. Tackling physical manufacturing problems will only work so far; offloading or streamlining performance and tracking Moore’s law will require blended software, hardware, and manufacturing processes.

Far from pessimistic Fryman believes making further progress using these techniques is do-able, if challenging, and offered a few directional examples including one on handling resiliency at small feature size.

“Everybody is worried that once you get down to 7 nm you are going to have higher variability and failures and what am I going to do about it. There are two ways to look at it. There are reactive measures, so if something fails, an ECC failure, a soft upset, what am I going to do about it? I’ll have to react, I’ll have to kill, I’ll have to restart,” said Fryman.

“There’s also the proactive side which is I am going to plan ahead for this future and I am going to design my system in software and the hardware level to periodically check itself, to check if I am leading to a failure situation should I bring down my voltage, should I migrate work away from something.

“From a user experience. I have a classic software layer. I’ve got run time sitting on top of hardware, how does that interact with the entire stack. I’ve got user codes. I’ve got runtimes. I’ve got programming support tools. All these things need to be aware of the underlying assumptions in the system,” he said.

Power management is another area likely to involve tighter links between software and hardware. He cited work from a Polaris test chip in the 2006-2007 timeframe. “I can look at fine grained power management techniques. This is another known technique that’s way beyond clock handling. There are 21 dynamic sleeper readings in the actual tile, a whole bunch of tiles on the die, and you let the system turn the tiles on and off in the sleep state, which give a significant energy savings.”

Fryman again emphasized this is known technique but it’s hard do because it extends beyond hardware and has software implications: how do you structure your code, how do you know when you can take advantage of something like this, etc.

“We are going to have to start thinking outside the box and [in many instances] go back to existing techniques and say so, do we really need cache coherency across an entire machine. Maybe not. Do we really need cache coherency across 1000 cores on a die or 100 cores on a die, probably not. Are we willing to take the complexity from software for a simpler more efficient, more scalable hardware? Really what I am saying moving forward is we need to take your heads out of the sand, pardon the pun, and rethink what we have been doing,” he said.

Fryman says the industry is moving into another era that he calls “the disaggregation of the datacenter.” In a fully connected model, he said, there is “no system you can design that can get the bandwidth.” More and more compute will push out to the edges and “it will look different and this is where machine learning an other algorithms come in and neuromorphic might be a big deal. I see the industry not as stagnant but going through this shift to the edge, which is a very different design point than the classic PC or tablet.”

The Intel engineer was careful not to reveal too much, “Eventually turning the knob on transistors, as we have been doing, will not work. When that is is highly debatable, which is why I chuckle. I’m not supposed to talk about post 7 nm but I can simply say it’s actively being looked into.”

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industry updates delivered to you every week!

MLPerf Inference 4.0 Results Showcase GenAI; Nvidia Still Dominates

March 28, 2024

There were no startling surprises in the latest MLPerf Inference benchmark (4.0) results released yesterday. Two new workloads — Llama 2 and Stable Diffusion XL — were added to the benchmark suite as MLPerf continues Read more…

Q&A with Nvidia’s Chief of DGX Systems on the DGX-GB200 Rack-scale System

March 27, 2024

Pictures of Nvidia's new flagship mega-server, the DGX GB200, on the GTC show floor got favorable reactions on social media for the sheer amount of computing power it brings to artificial intelligence.  Nvidia's DGX Read more…

Call for Participation in Workshop on Potential NSF CISE Quantum Initiative

March 26, 2024

Editor’s Note: Next month there will be a workshop to discuss what a quantum initiative led by NSF’s Computer, Information Science and Engineering (CISE) directorate could entail. The details are posted below in a Ca Read more…

Waseda U. Researchers Reports New Quantum Algorithm for Speeding Optimization

March 25, 2024

Optimization problems cover a wide range of applications and are often cited as good candidates for quantum computing. However, the execution time for constrained combinatorial optimization applications on quantum device Read more…

NVLink: Faster Interconnects and Switches to Help Relieve Data Bottlenecks

March 25, 2024

Nvidia’s new Blackwell architecture may have stolen the show this week at the GPU Technology Conference in San Jose, California. But an emerging bottleneck at the network layer threatens to make bigger and brawnier pro Read more…

Who is David Blackwell?

March 22, 2024

During GTC24, co-founder and president of NVIDIA Jensen Huang unveiled the Blackwell GPU. This GPU itself is heavily optimized for AI work, boasting 192GB of HBM3E memory as well as the the ability to train 1 trillion pa Read more…

MLPerf Inference 4.0 Results Showcase GenAI; Nvidia Still Dominates

March 28, 2024

There were no startling surprises in the latest MLPerf Inference benchmark (4.0) results released yesterday. Two new workloads — Llama 2 and Stable Diffusion Read more…

Q&A with Nvidia’s Chief of DGX Systems on the DGX-GB200 Rack-scale System

March 27, 2024

Pictures of Nvidia's new flagship mega-server, the DGX GB200, on the GTC show floor got favorable reactions on social media for the sheer amount of computing po Read more…

NVLink: Faster Interconnects and Switches to Help Relieve Data Bottlenecks

March 25, 2024

Nvidia’s new Blackwell architecture may have stolen the show this week at the GPU Technology Conference in San Jose, California. But an emerging bottleneck at Read more…

Who is David Blackwell?

March 22, 2024

During GTC24, co-founder and president of NVIDIA Jensen Huang unveiled the Blackwell GPU. This GPU itself is heavily optimized for AI work, boasting 192GB of HB Read more…

Nvidia Looks to Accelerate GenAI Adoption with NIM

March 19, 2024

Today at the GPU Technology Conference, Nvidia launched a new offering aimed at helping customers quickly deploy their generative AI applications in a secure, s Read more…

The Generative AI Future Is Now, Nvidia’s Huang Says

March 19, 2024

We are in the early days of a transformative shift in how business gets done thanks to the advent of generative AI, according to Nvidia CEO and cofounder Jensen Read more…

Nvidia’s New Blackwell GPU Can Train AI Models with Trillions of Parameters

March 18, 2024

Nvidia's latest and fastest GPU, codenamed Blackwell, is here and will underpin the company's AI plans this year. The chip offers performance improvements from Read more…

Nvidia Showcases Quantum Cloud, Expanding Quantum Portfolio at GTC24

March 18, 2024

Nvidia’s barrage of quantum news at GTC24 this week includes new products, signature collaborations, and a new Nvidia Quantum Cloud for quantum developers. Wh Read more…

Alibaba Shuts Down its Quantum Computing Effort

November 30, 2023

In case you missed it, China’s e-commerce giant Alibaba has shut down its quantum computing research effort. It’s not entirely clear what drove the change. Read more…

Nvidia H100: Are 550,000 GPUs Enough for This Year?

August 17, 2023

The GPU Squeeze continues to place a premium on Nvidia H100 GPUs. In a recent Financial Times article, Nvidia reports that it expects to ship 550,000 of its lat Read more…

Shutterstock 1285747942

AMD’s Horsepower-packed MI300X GPU Beats Nvidia’s Upcoming H200

December 7, 2023

AMD and Nvidia are locked in an AI performance battle – much like the gaming GPU performance clash the companies have waged for decades. AMD has claimed it Read more…

DoD Takes a Long View of Quantum Computing

December 19, 2023

Given the large sums tied to expensive weapon systems – think $100-million-plus per F-35 fighter – it’s easy to forget the U.S. Department of Defense is a Read more…

Synopsys Eats Ansys: Does HPC Get Indigestion?

February 8, 2024

Recently, it was announced that Synopsys is buying HPC tool developer Ansys. Started in Pittsburgh, Pa., in 1970 as Swanson Analysis Systems, Inc. (SASI) by John Swanson (and eventually renamed), Ansys serves the CAE (Computer Aided Engineering)/multiphysics engineering simulation market. Read more…

Choosing the Right GPU for LLM Inference and Training

December 11, 2023

Accelerating the training and inference processes of deep learning models is crucial for unleashing their true potential and NVIDIA GPUs have emerged as a game- Read more…

Intel’s Server and PC Chip Development Will Blur After 2025

January 15, 2024

Intel's dealing with much more than chip rivals breathing down its neck; it is simultaneously integrating a bevy of new technologies such as chiplets, artificia Read more…

Baidu Exits Quantum, Closely Following Alibaba’s Earlier Move

January 5, 2024

Reuters reported this week that Baidu, China’s giant e-commerce and services provider, is exiting the quantum computing development arena. Reuters reported � Read more…

Leading Solution Providers

Contributors

Comparing NVIDIA A100 and NVIDIA L40S: Which GPU is Ideal for AI and Graphics-Intensive Workloads?

October 30, 2023

With long lead times for the NVIDIA H100 and A100 GPUs, many organizations are looking at the new NVIDIA L40S GPU, which it’s a new GPU optimized for AI and g Read more…

Shutterstock 1179408610

Google Addresses the Mysteries of Its Hypercomputer 

December 28, 2023

When Google launched its Hypercomputer earlier this month (December 2023), the first reaction was, "Say what?" It turns out that the Hypercomputer is Google's t Read more…

AMD MI3000A

How AMD May Get Across the CUDA Moat

October 5, 2023

When discussing GenAI, the term "GPU" almost always enters the conversation and the topic often moves toward performance and access. Interestingly, the word "GPU" is assumed to mean "Nvidia" products. (As an aside, the popular Nvidia hardware used in GenAI are not technically... Read more…

Shutterstock 1606064203

Meta’s Zuckerberg Puts Its AI Future in the Hands of 600,000 GPUs

January 25, 2024

In under two minutes, Meta's CEO, Mark Zuckerberg, laid out the company's AI plans, which included a plan to build an artificial intelligence system with the eq Read more…

Google Introduces ‘Hypercomputer’ to Its AI Infrastructure

December 11, 2023

Google ran out of monikers to describe its new AI system released on December 7. Supercomputer perhaps wasn't an apt description, so it settled on Hypercomputer Read more…

China Is All In on a RISC-V Future

January 8, 2024

The state of RISC-V in China was discussed in a recent report released by the Jamestown Foundation, a Washington, D.C.-based think tank. The report, entitled "E Read more…

Intel Won’t Have a Xeon Max Chip with New Emerald Rapids CPU

December 14, 2023

As expected, Intel officially announced its 5th generation Xeon server chips codenamed Emerald Rapids at an event in New York City, where the focus was really o Read more…

IBM Quantum Summit: Two New QPUs, Upgraded Qiskit, 10-year Roadmap and More

December 4, 2023

IBM kicks off its annual Quantum Summit today and will announce a broad range of advances including its much-anticipated 1121-qubit Condor QPU, a smaller 133-qu Read more…

  • arrow
  • Click Here for More Headlines
  • arrow
HPCwire