Researchers Shrink Transistor Gate to One Nanometer

By Tiffany Trader

October 13, 2016

lbnl_transistor_schematic_desaiA team of US scientists may have just breathed new life into a faltering Moore’s law and advanced the goalposts for microelectronic miniaturization with the fabrication of a transistor with a 1nm gate. The implementation relies on the layered semiconductor molybdenum disulfide (MoS2) as an alternative to silicon.

The breakthrough portends a path beyond silicon-based transistors, which have been widely predicted to hit a wall at 5-nanometers. Current process technology runs between 14-22nm with 10nm devices under commercial development and expected to start shipping in 2017.

The difficulties of sub-5nm scaling coincided with the dissolution of the International Technology Roadmap for Semiconductors (ITRS) in July. In their final report, the authors said traditional transistor scaling (through smaller feature sizes) would likely hit an economic wall in 2021 at the 5-nm mark. After that, vertical scaling should provide further gains out to 2030, they guided.

“The semiconductor industry has long assumed that any gate below 5 nanometers wouldn’t work, so anything below that was not even considered,” said Sujay Desai, a researcher at the University of California, Berkeley, lead author of a paper detailing the 1nm transistor, published in the journal Science. “This research shows that sub-5-nanometer gates should not be discounted.”

To build their miniature marvel, scientists from Lawrence Berkeley National Laboratory, Stanford University, and the University of Texas at Dallas constructed the gate out of carbon nanotubes and used molybdenum disulfide (MoS2), a common engine lubricant, as the semiconductor material.

To create a functional gate at the atomic scale researchers needed to counter a phenomenon known as quantum tunneling, in which the barrier becomes porous to electrons. In the case of silicon transistors, tunneling along with loss of electrostatic control has lead to unacceptable leakage current when the device is off, the researchers explain.

While electrons flow easily through silicon, in MoS2 they are sufficiently slowed down to ensure they don’t come crashing through the ultra-thin gate. Using layers just .65 nm thick, MoS2 also achieves a lower dielectric constant. The electrical properties combined with the heavier effective carrier mass of MoS2 demonstrate a superior leakage control mechanism compared with traditional silicon semiconductors.

“These ultrashort devices exhibit excellent switching characteristics with near ideal subthreshold swing of ~65 millivolts per decade and an On/Off current ratio of ~106,” the research team writes. “Simulations show an effective channel length of ~3.9 nm in the Off state and ~1 nm in the On state.”

You can read more about the project here, or go directly here to access the Science paper, “MoS2 transistors with 1-nanometer gate lengths.”

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