STREAM Benchmark Author McCalpin Traces System Balance Trends

By Tiffany Trader

November 7, 2016

When Dr. John D. McCalpin introduced the STREAM benchmark in 1991, it had already become become clear that peak arithmetic rate was not an adequate measure of system performance for many applications. Since then, CPU performance has continued to outpace memory performance measures, leading to the processor-memory speed gap, known as the memory wall. In an invited talk at SC16, McCalpin will review the history of the changing “balances” between computation, memory latency, and memory bandwidth in HPC systems and will address the implications for the coming generation of systems.

Ahead of his talk at SC16, McCalpin gives us a peak into his activities at TACC, where he holds posts as HPC research scientist and co-director of ACElab, and provides an in-depth commentary on the dynamics between compute and memory in the context of the evolving HPC landscape.

HPCwire: What is the focus of your work at the Texas Advanced Computing Center (TACC)? 

Dr. John D. McCalpin: My work at TACC is primarily focused on understanding the performance characteristics of current and forthcoming hardware, and understanding the interactions between the hardware and the applications that we have identified as making up important parts of the workloads for TACC’s HPC-oriented systems. This involves a great deal of “detective work” – designing microbenchmarks to test various hypotheses about how the machines actually work at a low level, and designing tests to understand whether the hardware performance counters are counting what we think they are counting. The hardware performance counters that are useful are then used to track performance characteristics of all jobs run on our systems, which is useful for both finding misconfigured jobs and for finding out which attributes of the system are important for various application areas.

HPCwire: TACC has such a diverse array of HPC machines. I imagine that having access to many different architectures is important to your research. 

McCalpin: Diversity is clearly both a blessing and a curse. The good part of diversity is being able to test different system configurations and interconnect fabrics and allocate users to systems that are configured appropriately for their workloads. The bad part of diversity is having to deal with surprisingly large differences in nomenclature and software infrastructure (especially with respect to BIOS options) across vendors – even for identical processors. In addition to being able to test codes on different systems, a very useful tool has been the ability to control CPU frequency and memory frequency independently with recent processors. This allows us to run sensitivity-based performance analyses for a lot more codes than we would be able to analyze manually, and allows us to characterize applications even without subject-area expertise on staff.

HPCwire: Your upcoming talk at SC16 is titled “Memory Bandwidth and System Balance in HPC Systems” – what is your thesis?

McCalpin: My goal in this talk is to help people in the HPC community become aware of the extreme changes in HPC hardware over the last decade, and to argue that major architectural changes are needed to allow performance and price/performance to improve as rapidly as the underlying technology could allow. In some ways 2016-era HPC hardware looks like 2006-era HPC hardware – dominated by 2-socket commodity (x86) servers with a high-performance (typically InfiniBand) interconnect. At a lower level there has been an immense increase in hardware complexity to support the design goal of nearly-constant peak memory bandwidth per core, and it is this complexity that makes our current systems both incredibly difficult to understand and fundamentally ill-suited as starting points for either significant price reduction or significant power reduction.

sustained-memory-bw-falling-graph-mccalpin-1000x
Trends in the relative performance of floating-point arithmetic and several classes of data access for select HPC servers over the past 25 years. Source: John McCalpin

HPCwire: How have the dynamics between compute and memory evolved over time?

McCalpin: This is not an easy topic to summarize, but a few themes are worth noting. The first is that the HPC market has experienced several “disruptive technology” transitions, in which technology that was inferior in performance, but dramatically cheaper, replaced the dominant technology. We saw this happen in the mid-1990’s when RISC microprocessor-based systems displaced the traditional vector systems, and again starting around 2004 when x86-based systems displaced the RISC systems. A second recurring theme is the divergence between the high growth rate of FLOPS per core and the lower (or absent) growth rate in sustained memory bandwidth per core within each era. In the x86-multicore era of the last decade, the number of cores per package has increased and the sustained bandwidth per package has increased at about the same rate, but with constant (or slightly increasing) memory latency. This provides the third theme – the rapidly increasing relative cost of memory latency relative to computation. The approximately constant memory latency also drives the fourth theme – the overwhelming dominance of memory concurrency in determining sustained bandwidth. With sustained processor performance almost flat, compute performance is largely determined by how many cores you are able to use. With memory latency about flat, memory bandwidth per package is largely determined by how many outstanding cache misses you can generate.

HPCwire: In what ways will exascale further challenge system balance?

McCalpin: The traditional design point of “1 Byte/second per FLOP/second” does not look possible for exascale systems with current technology trends – both the purchase price and the power consumption are too high. The straight-line projection for exascale points to systems with extremely high compute capability per unit of bandwidth. These will be effective for a very limited number of applications. In the absence of a solid “general-purpose” design point, a more focused fallback position may be to develop multiple “special-purpose” systems, with architectures and implementations customized for a small number of particular applications of interest. This would allow substituting hundreds of millions of dollars of design and implementation expense for hundreds of millions of dollars of “general-purpose” hardware that is not well-matched to the specific application requirements.

HPCwire: What class of high-performance computer is best positioned to address memory bottlenecks?

HPC has been dominated by clusters of two-socket x86 nodes, which definitely have an easier time of providing bandwidth than larger SMP nodes. There are several reasons to believe that this design point has been pushed about as far as possible, and the introduction of a new layer of high-speed in-package memory will provide strong motivation to switch to single-socket nodes to eliminate off-chip cache coherence traffic. More radical possibilities will also be required (discussed below), but it is less clear how long that more painful transition can be put off.

HPCwire: Are you seeing advances on the algorithm and programming side to minimize data costs?

McCalpin: There has been some improvement in many application areas simply because more complex simulations are naturally more computationally dense, and therefore more likely to be limited by computation and less likely to be limited by memory access. This improvement has been partly deliberate, but also largely accidental – a happy byproduct of moving to more complex problems. Some applications can tolerate high memory access costs, but for applications that are not compute-bound we are significantly burdened by hardware architectures that do not allow data motion to be visible or controlled. This was the right answer in 1990, when arithmetic was much more expensive than memory reference, but in the current technology regime it is only justifiable by compatibility with the huge installed base of code – it would certainly not be the way to design an architecture for current technology balances or for expected technology balances in the remainder of the CMOS era. There have been attempts to provide programming languages and models to address data motion, but these have not been successful – programming languages can’t exploit hardware features that don’t exist, and can’t control behavior that is intended to be invisible. For many of the same reasons, we also tolerate architectures that are not energy-efficient because high per-node purchase prices have kept the energy costs relatively small (typically 5-7 percent of the initial purchase price per year of operation).

HPCwire: You introduced the STREAM Benchmark in 1991 — what is it and what trends have you documented?

McCalpin: The STREAM benchmark is a very simple, self-contained benchmark code (in C or Fortran) that measures the rate at which a system can perform four simple long-vector operations on floating-point numbers. For systems with caches, the standard way to configure the benchmark is to select an array size such that each of the three arrays used is much larger than the available cache(s), so that essentially all of the data accesses result in reads from memory or writes to memory. The benchmark is set up to time each iteration of each kernel and print out the computed memory access rate (reads + writes) for the fastest iteration of each kernel. When users are kind enough to submit results for publication, I add information that allows me to compute peak arithmetic performance and the balance between peak compute rates and sustained bandwidth. STREAM has been instrumental in getting vendors to pay attention to sustained, rather than peak, bandwidths, and the almost 1100 results in the database provide documentation of the trends and transitions I addressed above.

HPCwire: What is the path forward — are there technologies on the horizon that address the system imbalance issues that you’ve outlined?

McCalpin: It is important to note that “imbalance” is a relative term – in this case “relative” to the demands of the applications of interest. There are major application areas that are not yet experiencing performance limitations due to memory latency or sustained memory bandwidth. On the other hand, as the balances shift, applications that used to be completely compute-limited may now be strongly bandwidth-limited on current systems. (An excellent example of this is the local-area weather code WRF – when I reviewed it in 2006 on dual-core Opteron systems the execution-time breakdown was about 30 percent memory access and 70 percent compute, but when I reviewed performance on Xeon E5 v3 processors (c. 2015) this breakdown had reversed to 70 percent memory access time and 30 percent compute time.) Emerging technologies such as stacked DRAM provide the ability to push more data through a chip, but not at low cost and not at low power. Basic physics makes it clear lower cost and lower power can only come from slower, simpler processors distributed across the system in close proximity to the elements of the distributed memory. This approach requires a low-cost, high-performance interconnect fabric that is designed to support low-overhead data motion and synchronization. A much larger challenge is the development of high-productivity programming languages and models that can effectively map to such a massively parallel, heterogeneous, distributed hardware platform.

john-mccalpin-150x150Dr. John D. McCalpin is a Research Scientist in the High Performance Computing Group and Co-Director of ACElab at TACC of the University of Texas at Austin. At TACC, he works on performance analysis and performance modeling in support of both current users and future system acquisitions.

Dr. McCalpin will be speaking at SC16 on Wednesday, November 16th, from 4:15pm – 5pm in Ballroom-EFGHIJ at the Salt Palace Convention Center.

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

Why HPC Storage Matters More Now Than Ever: Analyst Q&A

September 17, 2021

With soaring data volumes and insatiable computing driving nearly every facet of economic, social and scientific progress, data storage is seizing the spotlight. Hyperion Research analyst and noted storage expert Mark No Read more…

GigaIO Gets $14.7M in Series B Funding to Expand Its Composable Fabric Technology to Customers

September 16, 2021

Just before the COVID-19 pandemic began in March 2020, GigaIO introduced its Universal Composable Fabric technology, which allows enterprises to bring together any HPC and AI resources and integrate them with networking, Read more…

What’s New in HPC Research: Solar Power, ExaWorks, Optane & More

September 16, 2021

In this regular feature, HPCwire highlights newly published research in the high-performance computing community and related domains. From parallel programming to exascale to quantum computing, the details are here. Read more…

Cerebras Brings Its Wafer-Scale Engine AI System to the Cloud

September 16, 2021

Five months ago, when Cerebras Systems debuted its second-generation wafer-scale silicon system (CS-2), co-founder and CEO Andrew Feldman hinted of the company’s coming cloud plans, and now those plans have come to fruition. Today, Cerebras and Cirrascale Cloud Services are launching... Read more…

AI Hardware Summit: Panel on Memory Looks Forward

September 15, 2021

What will system memory look like in five years? Good question. While Monday's panel, Designing AI Super-Chips at the Speed of Memory, at the AI Hardware Summit, tackled several topics, the panelists also took a brief glimpse into the future. Unlike compute, storage and networking, which... Read more…

AWS Solution Channel

Supporting Climate Model Simulations to Accelerate Climate Science

The Amazon Sustainability Data Initiative (ASDI), AWS is donating cloud resources, technical support, and access to scalable infrastructure and fast networking providing high performance computing (HPC) solutions to support simulations of near-term climate using the National Center for Atmospheric Research (NCAR) Community Earth System Model Version 2 (CESM2) and its Whole Atmosphere Community Climate Model (WACCM). Read more…

ECMWF Opens Bologna Datacenter in Preparation for Atos Supercomputer

September 14, 2021

In January 2020, the European Centre for Medium-Range Weather Forecasts (ECMWF) – a juggernaut in the weather forecasting scene – signed a four-year, $89-million contract with European tech firm Atos to quintuple its supercomputing capacity. With the deal approaching the two-year mark, ECMWF... Read more…

Why HPC Storage Matters More Now Than Ever: Analyst Q&A

September 17, 2021

With soaring data volumes and insatiable computing driving nearly every facet of economic, social and scientific progress, data storage is seizing the spotlight Read more…

Cerebras Brings Its Wafer-Scale Engine AI System to the Cloud

September 16, 2021

Five months ago, when Cerebras Systems debuted its second-generation wafer-scale silicon system (CS-2), co-founder and CEO Andrew Feldman hinted of the company’s coming cloud plans, and now those plans have come to fruition. Today, Cerebras and Cirrascale Cloud Services are launching... Read more…

AI Hardware Summit: Panel on Memory Looks Forward

September 15, 2021

What will system memory look like in five years? Good question. While Monday's panel, Designing AI Super-Chips at the Speed of Memory, at the AI Hardware Summit, tackled several topics, the panelists also took a brief glimpse into the future. Unlike compute, storage and networking, which... Read more…

ECMWF Opens Bologna Datacenter in Preparation for Atos Supercomputer

September 14, 2021

In January 2020, the European Centre for Medium-Range Weather Forecasts (ECMWF) – a juggernaut in the weather forecasting scene – signed a four-year, $89-million contract with European tech firm Atos to quintuple its supercomputing capacity. With the deal approaching the two-year mark, ECMWF... Read more…

Quantum Computer Market Headed to $830M in 2024

September 13, 2021

What is one to make of the quantum computing market? Energized (lots of funding) but still chaotic and advancing in unpredictable ways (e.g. competing qubit tec Read more…

Amazon, NCAR, SilverLining Team for Unprecedented Cloud Climate Simulations

September 10, 2021

Earth’s climate is, to put it mildly, not in a good place. In the wake of a damning report from the Intergovernmental Panel on Climate Change (IPCC), scientis Read more…

After Roadblocks and Renewals, EuroHPC Targets a Bigger, Quantum Future

September 9, 2021

The EuroHPC Joint Undertaking (JU) was formalized in 2018, beginning a new era of European supercomputing that began to bear fruit this year with the launch of several of the first EuroHPC systems. The undertaking, however, has not been without its speed bumps, and the Union faces an uphill... Read more…

How Argonne Is Preparing for Exascale in 2022

September 8, 2021

Additional details came to light on Argonne National Laboratory’s preparation for the 2022 Aurora exascale-class supercomputer, during the HPC User Forum, held virtually this week on account of pandemic. Exascale Computing Project director Doug Kothe reviewed some of the 'early exascale hardware' at Argonne, Oak Ridge and NERSC (Perlmutter), while Ti Leggett, Deputy Project Director & Deputy Director... Read more…

Ahead of ‘Dojo,’ Tesla Reveals Its Massive Precursor Supercomputer

June 22, 2021

In spring 2019, Tesla made cryptic reference to a project called Dojo, a “super-powerful training computer” for video data processing. Then, in summer 2020, Tesla CEO Elon Musk tweeted: “Tesla is developing a [neural network] training computer called Dojo to process truly vast amounts of video data. It’s a beast! … A truly useful exaflop at de facto FP32.” Read more…

Berkeley Lab Debuts Perlmutter, World’s Fastest AI Supercomputer

May 27, 2021

A ribbon-cutting ceremony held virtually at Berkeley Lab's National Energy Research Scientific Computing Center (NERSC) today marked the official launch of Perlmutter – aka NERSC-9 – the GPU-accelerated supercomputer built by HPE in partnership with Nvidia and AMD. Read more…

Esperanto, Silicon in Hand, Champions the Efficiency of Its 1,092-Core RISC-V Chip

August 27, 2021

Esperanto Technologies made waves last December when it announced ET-SoC-1, a new RISC-V-based chip aimed at machine learning that packed nearly 1,100 cores onto a package small enough to fit six times over on a single PCIe card. Now, Esperanto is back, silicon in-hand and taking aim... Read more…

Enter Dojo: Tesla Reveals Design for Modular Supercomputer & D1 Chip

August 20, 2021

Two months ago, Tesla revealed a massive GPU cluster that it said was “roughly the number five supercomputer in the world,” and which was just a precursor to Tesla’s real supercomputing moonshot: the long-rumored, little-detailed Dojo system. “We’ve been scaling our neural network training compute dramatically over the last few years,” said Milan Kovac, Tesla’s director of autopilot engineering. Read more…

CentOS Replacement Rocky Linux Is Now in GA and Under Independent Control

June 21, 2021

The Rocky Enterprise Software Foundation (RESF) is announcing the general availability of Rocky Linux, release 8.4, designed as a drop-in replacement for the soon-to-be discontinued CentOS. The GA release is launching six-and-a-half months after Red Hat deprecated its support for the widely popular, free CentOS server operating system. The Rocky Linux development effort... Read more…

Google Launches TPU v4 AI Chips

May 20, 2021

Google CEO Sundar Pichai spoke for only one minute and 42 seconds about the company’s latest TPU v4 Tensor Processing Units during his keynote at the Google I Read more…

Intel Completes LLVM Adoption; Will End Updates to Classic C/C++ Compilers in Future

August 10, 2021

Intel reported in a blog this week that its adoption of the open source LLVM architecture for Intel’s C/C++ compiler is complete. The transition is part of In Read more…

AMD-Xilinx Deal Gains UK, EU Approvals — China’s Decision Still Pending

July 1, 2021

AMD’s planned acquisition of FPGA maker Xilinx is now in the hands of Chinese regulators after needed antitrust approvals for the $35 billion deal were receiv Read more…

Leading Solution Providers

Contributors

Hot Chips: Here Come the DPUs and IPUs from Arm, Nvidia and Intel

August 25, 2021

The emergence of data processing units (DPU) and infrastructure processing units (IPU) as potentially important pieces in cloud and datacenter architectures was Read more…

Julia Update: Adoption Keeps Climbing; Is It a Python Challenger?

January 13, 2021

The rapid adoption of Julia, the open source, high level programing language with roots at MIT, shows no sign of slowing according to data from Julialang.org. I Read more…

10nm, 7nm, 5nm…. Should the Chip Nanometer Metric Be Replaced?

June 1, 2020

The biggest cool factor in server chips is the nanometer. AMD beating Intel to a CPU built on a 7nm process node* – with 5nm and 3nm on the way – has been i Read more…

HPE Wins $2B GreenLake HPC-as-a-Service Deal with NSA

September 1, 2021

In the heated, oft-contentious, government IT space, HPE has won a massive $2 billion contract to provide HPC and AI services to the United States’ National Security Agency (NSA). Following on the heels of the now-canceled $10 billion JEDI contract (reissued as JWCC) and a $10 billion... Read more…

Quantum Roundup: IBM, Rigetti, Phasecraft, Oxford QC, China, and More

July 13, 2021

IBM yesterday announced a proof for a quantum ML algorithm. A week ago, it unveiled a new topology for its quantum processors. Last Friday, the Technical Univer Read more…

Intel Launches 10nm ‘Ice Lake’ Datacenter CPU with Up to 40 Cores

April 6, 2021

The wait is over. Today Intel officially launched its 10nm datacenter CPU, the third-generation Intel Xeon Scalable processor, codenamed Ice Lake. With up to 40 Read more…

Frontier to Meet 20MW Exascale Power Target Set by DARPA in 2008

July 14, 2021

After more than a decade of planning, the United States’ first exascale computer, Frontier, is set to arrive at Oak Ridge National Laboratory (ORNL) later this year. Crossing this “1,000x” horizon required overcoming four major challenges: power demand, reliability, extreme parallelism and data movement. Read more…

Intel Unveils New Node Names; Sapphire Rapids Is Now an ‘Intel 7’ CPU

July 27, 2021

What's a preeminent chip company to do when its process node technology lags the competition by (roughly) one generation, but outmoded naming conventions make it seem like it's two nodes behind? For Intel, the response was to change how it refers to its nodes with the aim of better reflecting its positioning within the leadership semiconductor manufacturing space. Intel revealed its new node nomenclature, and... Read more…

  • arrow
  • Click Here for More Headlines
  • arrow
HPCwire