On Monday at SC16 the 1st International Workshop on Post-Moore Era Supercomputing (PMES) will dive into the world of tomorrow. On Wednesday it will be followed by a distinguished panel, Post Moore’s Era Supercomputing in 20 Years, digging into some of the ideas explored at the workshop. These kinds of sessions are always fun and considering the panel participants, this one should be fascinating.
Panel moderator Jeffrey Vetter, leader of Oak Ridge National Laboratory’s Future Technology Group, says 41 papers were submitted for the workshop and eventually whittled down to 15. In this brief Q&A, Vetter sets the stage for what the workshop and panel hope to tackle and offers a few ideas of his own. Here’s the list of panelists:
- Jeffrey S. Vetter (ORNL)
- Keren Bergman (Columbia University)
- Tom Conte (Georgia Institute of Technology)
- Erik DeBenedictis (Sandia National Laboratories)
- Satoshi Matsuoka (Tokyo Institute of Technology)
- John Shalf (Lawrence Berkeley National Laboratory)
- George Michelogiannakis (Lawrence Berkeley National Laboratory)
- Jun Sawada (IBM)
- Matthias Troyer (ETH, Zurich)
HPCWire: Technology crystal ball gazing is always fun. What are the broad goals of the panel and what key issues you think need to be addressed? Maybe comment on the workshop and how it will inform panel and perhaps on why the specific panelists were selected (if appropriate).
Jeffrey Vetter: Our goal with this panel is to discuss the potential opportunities and challenges for Post Moore technologies from the perspective of the HPC community. HPC occupies a different portion of the design space than other options like enterprise or mobile.
The Post Moore’s Era Supercomputing (PMES) design space is very broad, and our PMES organizing committee decided to have very broad criteria for submissions in order to show a diversity of potential solutions. As a result, in our upcoming workshop, we have accepted papers on neuromorphic computing, adiabatic quantum computing, approximate computing, reconfigurable computing, software and performance modeling for PMES systems, and a few others. We hope that the audience can learn more about these topics, and make their own assessment of these technologies.
HPCWire: Quantum computing and neuromorphic computing are frequently discussed as game-changers moving forward. When you look at these two (sort of) emerging technologies how would you characterize their strengths, shortcomings, and needed advances to become key players going forward?
Vetter: Indeed. Quantum computing and neuromorphic computing have had recent successes. The concepts for these technologies have been around for two decades or more. Recently, we have seen some interesting experiments and progress.
Quantum computing has incredible possibilities, starting with Shor’s initial paper on factoring, and, now, with recent work in other algorithms. However, the goal of creating a scalable computing system from thousands (or more) of qubits remains an open research question. Manufacturing and controlling just a few qubits still has challenges like fine-grained quantum error correction, and building a very complex classical electronic control system to manage the qubits. Aside from the system itself, we need mission critical applications and programming concepts that can exploit this new technology.
Neuromorphic computing has seen tremendous progress in the past five years with systems like True North and SpiNNaker. Much of this work uses traditional CMOS digital electronics to emulate aspects of brain-inspired computing, like neurons and synapses. Even though these systems must be trained offline, they can have exceptional performance and energy efficiency. Recently, researchers have been exploring the use of memristors to implement this functionality, including online training, and they look promising. Two PMES papers illustrate these approaches.
HPCWire: How far can existing technology (CMOS and perhaps other process-friendly materials) take us? There are reports Samsung has beaten Intel to 10nm technology and at ISC16 Intel presenter Josh Fryman said the company is actively looking at “post 7 nm” technology.
Vetter: I believe that we will have CMOS devices indefinitely; it is an exceptional technology! In other words, even though device scaling will stop at some point with CMOS, I believe that it will continue to provide significant value, occupying an important rung on our technology ladder, until unseated by some disruptive technology.
A potentially more important consequence is that of economic and business strategies. The past year has been chaotic and illustrative as we have seen some of the largest semiconductor business deals ever: Softbank acquiring ARM, Qualcomm acquiring NXP, Intel acquiring Altera, Avago acquiring Broadcom, Broadcom acquiring Brocade, Western Digital acquiring SanDisk, etc. Many of these deals are being driven by economies of scale in design, engineering, and manufacturing costs. This may be the ultimate halting condition. It will be interesting to see who goes next.
HPCWire: Power is a huge issue. Supercomputing needs too much – rather amazing the brain does with 10-20W what SCs need MW for. How do you see that challenge being addressed and what are some of the emerging avenues that look promising?
Vetter: We are already experiencing an important transition in memory systems to non-volatile memory (NVM), due in part to cost and energy efficiency. Consumer and enterprise systems have been using NVM for quite some time, but 3D NAND flash is emerging to be the dominate memory type (including DRAM) available in nearly every computing architecture. Future NVM devices, like memristors, phase-change memory, and the Intel/Micron Xpoint memory, may have benefits over flash memory, which will allow engineers to integrate NVM even closer to the processor, up the memory hierarchy.
HPCWire: All this computing power needs to be able to do real work, something I know that is close to the heart of ORNL’s FTG team. What’s your take on the software challenge, in particular application software, and what/how should efforts (maybe co-design) be mounted to solve them?
Yes, in my opinion, programming systems and application performance portability are the most critical challenges for the HPC community today. We cannot expect the applications teams to rewrite major portions of their applications as every new hardware technology emerges. Our applications exist for years, if not decades. Our group has been investigating how to extend existing programming models, like OpenACC and the C language to include FPGAs and NVM, respectively. However, this problem is very complex and challenging; it will take our community working over years to propose and agree on solutions.
HPCWire: The 20-year window cited in the Panel title is, shall we say ambitious? Surprises will occur. From a more speculative perspective, what are some blue-sky ideas around supercomputing in the next two decades to consider. What technologies do you think have a chance – however slim or however barely worked upon now – to be disrupters?
Vetter: Hopefully, our PMES workshop and panel will help provide the SC community with a view into the potential benefits and challenges of some of these technologies: quantum, neuromorphic, silicon photonics, reconfigurable, etc. Countless numbers of smart people are working on solutions to these problems, but many technologies never mature to the level that they can be deployed effectively in a production environment. Nascent technologies like computing with carbon nanotubes, DNA, and various other nanotechnologies are very exciting, but they are also very immature. Like quantum and neuromorphic computing, researchers started work on the conceptual underpinnings for these technologies years ago; however, most of them have limitations in some key area, like manufacturing process, reliability, cost, etc. As the environment and assumptions change, we need to revisit these technologies to evaluate their possibilities.