Moving Just to Exascale or Preparing for Sustained Scaling?

By Thomas Sterling

November 11, 2016

Editor’s Note: In this guest article, Thomas Sterling, director of the Center for Research in Extreme Scale Technologies and Professor of Electrical Engineering” at the “Department of Intelligent Systems Engineering” at Indiana University, wonders whether the quest for exascale is in danger of underachieving even if it hits the literal goal. A broader vision and approach, he suggests, is needed. He explores how runtime system software, for example, might play a role in helping the race for exascale move beyond simple von Neumann incrementalism and tackle more substantive changes that enhance scalability more generally.

Sterling has three events at SC this year, his talk HPC Runtime System Software for Asynchronous Multi-Tasking (Thurs.), participation on the panel HPC Workforce Development: How Do We Find Them, Recruit Them, and Teach Them to Be Today’s Practitioners and Tomorrow’s Leaders? (Tues.), and a keynote address at the 2nd International Workshop on Extreme Scale Programming Models and Middleware (Fri.) – John Russell

Forward looking thinkers and programs are setting the course of the nation and internationally towards the acclaimed achievement of exascale computing. The value to important application domains from multi-physics simulation to societal data analytics and the wide range of problems encompassed hardly needs explaining to this community. Even the criterion of exascale – which is poorly defined at best and need not be dwelt upon as a qualitative sense of the goal or goals associated with the rubric of “exascale” – is sufficient to challenge hardware and software engineers as well as end users to push technologies and methods, at least incrementally, in the direction of orders of magnitude gain beyond the 2015 baselines.

But there is a significant difference between forcing systems capability towards an admittedly arbitrary Rmax number and setting a long-term path across the entire expanse of what might be characterized as the “exascale performance regime” spanning the 1000X computing frontier from Exaops to Zettaops. There is a distinct difference in approach between dragging the past through patchwork incrementalism to achieve the shorter term goal at minimum cost and apparent convenience versus setting the new course of computing system class through which a dramatic range of computing may be traversed over time (e.g., through 2035). To achieve the latter demands the identification and formulation of untapped principles based on opportunities consistent with the physics of emerging technologies and responsive to their limiting factors. Some such principles may extend back decades to assumptions that have gone largely unquestioned to this day even though the underlying motivations for these have largely dispersed. Others may have been recognized or even applied but within the wrong contexts to be profitable for HPC. Two such domains of pursuit briefly considered in this article during the week of SC16 are the emergent application and implementation of runtime system software and superseding reliance on von Neumann derivatives for architecture.

This discussion is not to be considered as a criticism of what is being planned for immediate nationally driven programs such as the DOE Exascale Computing Project (ECP). Rather it is intended to note, as many have, that the changing conditions related to Moore’s law and power constrained clock rates as well as poor efficiency and scalability of at least strong-scaled problems today demand renewed research beyond the short-term and conventional. As our nation and the world organizes to develop systems capable of exascale computing aligned with the National Strategic Computing Initiative in the areas both of numeric and data analytics solutions, hard choices are being made in terms of technical, conceptual and programmatic approaches and where research investments if any are to be made. Practical considerations include limited budgets, sustained continuity of mission critical legacy codes, risk avoidance and mitigation, and subjective biases towards familiar programming methods and industry architecture roadmaps. These pragmatic concerns are yielding somewhat conservative plans to achieving still yet ill-defined metrics of exascale rather than establishing the launch vector towards the entire performance regime of the next four orders of magnitude. From the outside peering into the sometimes opaque planning offices, it appears that research funding is being sacrificed in the name of risk minimization and “curiosity driven research” especially in the area of systems.To stimulate a renewal of more advanced exploration needed to achieve better than the bare minimum of performance goals, these comments briefly discuss two areas of consideration: 1) the emergence of runtime systems in support of improved efficiency and scalability, and 2) unquestioned assumptions that continue to inhibit progress.

Runtime system software is being explored by a number of research teams nationally and internationally to exploit compute time information about application state and system usage for dynamic and adaptive introspective control of resource management and task scheduling. The potential of runtime systems is to achieve superior resource utilization, load balancing, data migration and affinity, and parallelism discovery. At its core, the impact of runtime system software is to change from conventional static practices to dynamic adaptive execution control. Depending on the specifics of the runtime software under consideration, a number of separate techniques that have been independently pursued over many years may be integrated within the runtime such as global address space, over decomposition, message-driven computation, multiple threading, and dataflow synchronization among other concepts. Their incorporation promises to reduce programmer burden and deliver performance portability across systems of different types, scales and generations. However, advanced scalable runtime systems are experimental and impose additional problems such as increased system software complexity, added overheads, and uncertainty about programming interfaces, support for legacy codes, and workload interoperability. Further, early results suggest that not all applications will benefit significantly through runtime support, with instances of performance reduction observed in certain cases.

Exploration of the set of opportunities for guided rather than ballistic computation offered by runtimes is found in such work at Charm++ at UIUC, OCR at Rice, HPX at LSU and ZTH, HPX-5 at Indiana University, DARMA at SNL, Legion at Stanford, and other projects in Europe and Japan. The lack of uniformity among the distinct approaches has inhibited application experiments and rapid optimization of system software resulting in calls for community standardization. While it is easy to sympathize with this, early standardization may be premature as experience with best practices is at its inchoate phase, such standards may be counterproductive, and actually impede rather than expedite progress. Focusing solely on runtimes without combined considerations of programming models, compiler roles, OS support, and even architecture implications may prove too narrow and also produce inadequate results. This has led the author in other contexts to propose a holistic approach based on full parallel execution models (e.g., ParalleX) to establish the mutual roles and responsibilities of all of the hardware and software layers, their interrelationships and their interfaces.

This strategy, while demonstrably effective based on variants of the communicating sequential processes model largely through MPI, had not been widely adopted in the creation of a new execution model that could provide the framework for effective exploitation of possible future runtime systems. It is the opinion of some that this will be necessary to break into the post Moore’s law era. Others, of course, point out that we have managed to struggle along without such revolutionary changes for two dozen years and such approaches would prove disruptive. There is some truth to both claims. Much more discussion on the details and issues of runtime system from trans-exascale computing will be presented in a future article. But a second aspect of achieving computing beyond exascale should be introduced as well: the opportunity for new hardware architectures even beyond the current roadmaps of the vendors.

Close examination exposes a litany of assumptions that have dominated HPC design and operation for decades. While at one time these constituted winning strategies, now they are counter to critical path objective functions. The actual list is long but here only a few under the topic of von Neumann derivatives will be considered. Essentially all commercially viable HPC system architectures over the last six decades and more have been derivative of the von Neumann architecture concept. From the original vacuum tube machines of the late 40’s and 50’s to the transistor machines of the 60’s, the SSI/MSI computers of the 70’s, the LSI systems of the 80’s, the VLSI systems of the 90’s, and the multicore chips of the last decade, the core elements reflect the basic principles of sequential instruction issue, the separation of logic from main memory (referred to as the “von Neumann bottleneck”, and the emphasis on ALU/FPU utilization as the primary point of optimization. Even with the many forms of parallelism that have been exploited as technology permitted such as pipelined execution, vectors, SIMD-arrays, and multiprocessing, von Neumann has been at the heart of execution control manifest in hardware, programming models and interfaces, and algorithms.

Each of these assumptions ingrained in current designs can be reconsidered to address the fundamental performance parameters that ultimately determine efficiency and scalability. These factors include the need to expose and exploit parallelism to overcome starvation of resources, particularly since the beginning of the multicore era in 2005. Latency effects have forced a conventional approach of deep memory hierarchies that rely on locality from data reuse. Overhead of software control bound the granularity of parallel tasks and therefore parallelism even as it wastes time and energy. And contention for shared resources, both physical and logical, impose bottlenecks and that may block precious resources. Those resources are no longer the FPUs but rather the means of data movement generally and into and out of the main memory in particular.

Research in architecture outside the mainstream has a long history but commercial competitive successes of the microprocessor epoch have hindered other than incremental approaches of improvement, the use of multi/many-core sockets, and GPUs. Nonetheless, with the flat-lining of so many important growth parameters, alternative architecture approaches that preclude the unquestioned assumptions presented earlier may have to be reconsidered. One is PIM or processor in memory that has its antecedents back to 1990 where the challenges of latency, parallelism and bandwidth may all be addressed. Here logic and memory blocks are integrated on the same semiconductor die to improve all these factors. Dataflow that extends back prior to 1980 provides important unifying lightweight parallelism control principles. While early architecture proposals failed to address the true implications of technology trends, the semantics are powerful and may lead to a new generation of managing multi-level granularity parallelism in the presence of asynchrony and latency mitigation as well as starvation. Finally, perhaps even a more remarkable suggestion is the examination of a class of cellular automata that has its genesis in 1949 and may be ideal for nano-scale hardware architecture for massive parallelism emphasizing memory bandwidth and making FPU capability a high availability rather than high utilization resource.

Here has only been touched on a space of future considerations and the potential for exploring alternatives to conventional assumptions and practices. There are no promises of superior capability but only of possibilities as yet unexplored under current technology trends. In the last half century I’ve been flying on commercial jet airliners, I have always been limited to subsonic speeds. Let’s hope we are not approaching a similar asymptote in HPC merely because of our failure to explore unknown approaches due to shortsighted vision or funding.

Author Bio

rp_Sterling-Thomas-2014-09-300x300.jpgDr. Thomas Sterling is Professor of Intelligent Systems Engineering at the Indiana University School of Informatics and Computing and Director of the Center for Research in Extreme Scale Technologies (CREST). Since receiving his Ph.D. from MIT in 1984 as a Hertz Fellow, Dr. Sterling has engaged in applied research in fields associated with parallel computing system structures, semantics, and operation in industry, government labs, and academia. Dr. Sterling is best known as the “father of Beowulf” for his pioneering research in commodity/Linux cluster computing, for which he shared the Gordon Bell Prize in 1997. He is the co-author of six books and holds six patents. He was the recipient of the 2013 Vanguard Award. In 2014, he was named a fellow of the American Association for the Advancement of Science.

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