If you are looking for guidance with programming and working with Intel’s Xeon Phi (Knights Landing) processors, a solid resource was posted today on the Partnership for Advanced Computing in Europe (PRACE) Researcher Infrastructure site: Best Practice Guide – Knights Landing, January 2017.
Given the rising availability of KNL-based systems from a growing numbers of vendors the guide may prove a useful support tool. It’s fairly comprehensive and was prepared by Vali Codreanu (SURFsara), Jorge Rodríguez (Barcelona Supercomputing Center), and Ole Widar Saastad (editor, University of Oslo).
Here’s an excerpt from the intro:
“This best practice guide provides information about Intel’s MIC architecture and programming models for the Intel Xeon Phi co-processor in order to enable programmers to achieve good performance of their applications. The guide covers a wide range of topics from the description of the hardware of the Intel Xeon Phi co-processor through information about the basic programming models as well as information about porting programs up to tools and strategies how to analyze and improve the performance of applications.”
And the table of contents linking to their sections:
- Introduction
- System Architecture / Configuration
- Programming Environment / Basic Porting
- Benchmark performance
- Application Performance
- Performance Analysis
- Tuning
- Debugging
As an example of the material, these charts and captions represent a tiny small snippet of the material in the memory portion of the Systems Architecture/Configuration section.
Here’s a link to the full guide: http://www.prace-ri.eu/best-practice-guide-knights-landing-january-2017/