Advancing Modular Supercomputing with DEEP and DEEP-ER Architectures

By Sean Thielen

February 24, 2017

Editor’s note: In this contributed feature, Sean Thielen details the innovative architectural concepts coming out of the DEEP and DEEP-ER projects, and follows the evolution of the Cluster-Booster architecture, a heterogeneous hardware design developed at the Jülich Supercomputing Centre.

Knowing that the jump to exascale will require novel architectural approaches capable of delivering dramatic efficiency and performance gains, researchers around the world are hard at work on next-generation HPC systems.

In Europe, the DEEP project has successfully built a next-generation heterogeneous architecture based on an innovative “cluster-booster” approach. The new architecture can dynamically assign individual code parts in a simulation to different hardware components based on which component can deliver the highest computational efficiency. It also provides a foundation for a modular type of supercomputing where a variety of top-level system components, such as a memory module or a data analytics module for example, could be swapped in and out based on workload characteristics. Recently, Norbert Eicker, head of the Cluster Computing research group at Jülich Supercomputing Centre (JSC), explained how the DEEP and DEEP-ER projects are advancing the idea of “modular supercomputing” in pursuit of exascale performance.

Why go DEEP?

Eicker says that the use of vectorization or multi-core processors have become the two main strategies for acceleration. He noted that the main advantages in general purpose multi-core processors include high single-thread performance due to relatively high frequency along with their ability to do out-of-order processing. Their downsides include limited energy efficiency and a higher cost per FLOP. Accelerators, such as the Intel Xeon Phi coprocessor or GPUs, on the other hand are more energy efficient but harder to program.

Given the different characteristics of general purpose processors and accelerators, it was only a matter for time before researchers began looking for ways to integrate different types of compute modules into an overall HPC system. Eicker said that most efforts have involved building heterogeneous clusters wherein standard cluster nodes are connected using a fabric and then accelerators are attached to each cluster node.

Figure 1: An example of a basic architecture for a heterogeneous cluster.

Per Eicker, this heterogeneous approach has drawbacks, including the need for static assignment of accelerators to CPUs. Since some applications benefit greatly from accelerators and others not at all, getting the ratio of CPUs to accelerators right is tricky and inevitably leads to inefficiencies. Eicker explained that the idea behind the DEEP project was to combine compute resources into a common fabric and make the accelerating resources more autonomous. The goal was to not only enable dynamic assignments between cluster nodes and the accelerator, but also to enable the accelerators to run a kind of MPI so the system could offload more complex kernels to the accelerators rather than needing to always rely on the CPU.

The building blocks of a successful prototype

Work on the prototype Dynamical Exascale Entry Platform (DEEP) system began in 2011, and was mostly finalized toward the end of 2015. It took the combined efforts of 20 partners to complete the European Commission funded project. The 500 TFLOP/s DEEP prototype system includes a “cluster” component with general-purpose Intel Xeon processors and a “booster” component with Intel Xeon Phi coprocessors along with a software stack capable of dynamically separating code parts in a simulation based on concurrency levels and sending them to the appropriate hardware component. The University of Heidelberg developed the fabric, which has been commercialized by EXTOLL and dubbed the EXTOLL 3D Torus Network.

Figure 2: The DEEP cluster-booster hardware architecture. The cluster is based on an Aurora HPC system from Eurotech. The booster includes 384 Intel Xeon Phi processors interconnected by Extoll fabric.

Given the unusual architecture, the project team knew it would need to modify and test applications from a variety of HPC fields on the DEEP system to prove its viability. The team analyzed each selected application to determine which parts would run better on the cluster and which would run better on the booster, and modified the applications accordingly. One example is a climate application from Cyprus Institute. The standard climate model part of the application runs on the cluster side while an atmospheric chemical simulation runs on the booster side, with both sides interacting with each other from time to time to exchange data.

The new software architecture

One of the most important developments of the DEEP project is a software architecture that includes new communication protocols for transferring data between network technologies, programming model extensions and other important advancements.

Figure 3: The DEEP software architecture includes standard software stack components along with some new components developed specifically for the project.

While left- and right-hand sides of the architecture in figure 3 are identical to the standard MPI-based software-stacks of most present day HPC architectures, the components in the middle add some important new capabilities. Eicker explained that in the DEEP software architecture, the main part of applications and less scalable code are only run on the cluster nodes and everything starts on the cluster side. What’s different is that the cluster part of the application can collectively start a crowd of MPI-processes on the right-hand side using a global MPI.

The spawn for the booster is a collective operation of cluster processes that creates an inter-communicator containing all parents on one side and all children on the other. For example, the MPI_COMM_WORLD or a subset of processes on the cluster side, collectively called the MPI_Comm_spawn function, can create a new MPI_COMM WORLD on the booster side that is capable of standard MPI communication. Once started, the processes on the booster side can communicate amongst each other and exchange messages, making it possible to offload complex kernels to the booster.

Using MPI to bridge between the different fabrics in the cluster and booster may seem like it would significantly complicate the lives of application developers. However, Barcelona Supercomputing Center invented what is basically a source-to-source compiler, called the OmpSs Offload Abstraction compiler that does much of the work. Developers see a familiar looking cluster side with an Infiniband-based MPI and a booster side with an EXTOLL-based MPI. Their job is to annotate the code to tell the compiler which parts should run on the cluster versus the booster. The OmpSs compiler introduces the MPI_Comm_spawn call and the other required communication calls for sharing data between the two code parts.

Eicker explained that the flexible DEEP approach has many advantages, including options for multiple operational modes that enable much more efficient use of system resources. Beyond the specialized symmetric mode described above, the booster can be used discretely, or as a pool of accelerators. He used applications that could scale on the Blue Gene system as an example, noting they be run entirely on the booster side with no cluster interaction.

From DEEP to DEEP-ER

Plans for the DEEP-ER (Dynamical Exascale Entry Platform – Extended Reach) phase include updating the booster to include the latest generation of Intel Xeon Phi processors. The team is also exploring how on-node Non-Volatile Memory (NVM), network attached memory and a simplified interface can improve the overall system capabilities.

Figure 4: The DEEP-ER cluster-booster hardware architecture.

Eicker said that since Xeon Phi processors are self-booting, the upgrade will make the hardware implementation easier. The team also significantly simplified the interface by using the EXTOLL fabric throughout the entire system. The global use of the EXTOLL fabric enabled the team to eliminate the booster interface nodes and the DEEP cluster-booster protocol. The DEEP-ER system will use a standard EXTOLL protocol running the two types of nodes. The EXTOLL interconnect also enables the system to take advantage of the network attached memory.

One of the main objectives of the DEEP-ER project is to explore scalable I/O. To that end, the project team is investigating the integration of different storage types, starting from the disks using NVM while also making use of the network attached memory. Eicker said the team is using the BeeGFS file system and extensions that enable smart caching to local NVMe devices in the common namespace of the file system to help improve performance as well as SIONlib, a scalable I/O library developed by JSC for parallel access to task-local files, to enable more efficient local tasking of I/O. Exascale10 I/O software from Seagate also sits on top of the BeeGFS file system, enabling the MPI I/O to make use of the file system cache extensions.

Beyond I/O, the DEEP-ER project is also exploring how to improve resiliency. Eicker noted that because the offloaded parts of programs are stateless in the DEEP approach, it’s possible to improve the overall resiliency of the software and make functions like checkpoint restart a lot more efficient than standard approaches.

Toward modular supercomputing

Each phase of the DEEP project is an important step forward toward modular supercomputing. Eicker said that the DEEP cluster-booster concept showed that it’s possible to integrate heterogeneous systems in new ways. With DEEP-ER, the combination of the NAM and network attached storage add what is essentially a memory booster module. Moving forward, there are all kinds of possibilities for new modules, according to Eicker. He mentioned an analytics module that might look like a cluster, but include more memory or different types of processors, or a module that acts as a graphics cluster for online visualization.

Figure 5: The end goal of the DEEP project is to create a truly modular supercomputer, which could pave the way for increasingly specialized modules for solving different types of supercomputing challenges.

The ultimate goal of the DEEP project is to build a flexible modular supercomputer that allows users to organize applications for efficient use of the various system modules. Eicker said that the DEEP-ER team hopes to extend its JURECA cluster with the next-generation Xeon Phi processor-based booster. Then the team will begin exploring new possibilities for the system, which could include adding new modules, such as a graphics, storage and data analytics modules. The next steps could even include a collaboration with the Human Brain Project on neuromorphic computing. And these ideas are only the beginning. The DEEP approach could enable scientists to dream up new modules for tackling their specific challenges. Eicker acknowledges that there is much work to be done, but he believes the co-design approach used by the DEEP team will continue to drive significant steps forward.

Watch a short video capturing highlights of Eicker’s presentation.

About the Author

Sean Thielen, the founder and owner of Sprocket Copy, is a freelance writer from Portland, Oregon who specializes in high-tech subject matter.

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

NSF Extends Access to Its Leadership Systems Blue Waters & Frontera

December 14, 2018

The National Science Foundation is seeking supplemental requests for access on its leadership-class computers Blue Waters and Frontera to enable "fundamental science and engineering research that would otherwise not be p Read more…

By Staff

CFD on ORNL’s Titan Simulates Cleaner, Low-MPG ‘Opposed Piston’ Engine

December 13, 2018

Pinnacle Engines is out to substantially improve vehicle gasoline efficiency and cut greenhouse gas emissions with a new motor based on an “opposed piston” design that the company hopes will be widely adopted while t Read more…

By Doug Black

Contract Signed for New Finnish Supercomputer

December 13, 2018

After the official contract signing yesterday, configuration details were made public for the new BullSequana system that the Finnish IT Center for Science (CSC) is procuring from Atos in two phases over the next year-an Read more…

By Tiffany Trader

HPE Extreme Performance Solutions

AI Can Be Scary. But Choosing the Wrong Partners Can Be Mortifying!

As you continue to dive deeper into AI, you will discover it is more than just deep learning. AI is an extremely complex set of machine learning, deep learning, reinforcement, and analytics algorithms with varying compute, storage, memory, and communications needs. Read more…

IBM Accelerated Insights

4 Ways AI Analytics Projects Fail — and How to Succeed

“How do I de-risk my AI-driven analytics projects?” This is a common question for organizations ready to modernize their analytics portfolio. Here are four ways AI analytics projects fail—and how you can ensure success. Read more…

Nvidia Leads Alpha MLPerf Benchmarking Round

December 12, 2018

Seven months after the launch of its AI benchmarking suite, the MLPerf consortium is releasing the first round of results based on submissions from Nvidia, Google and Intel. Of the seven benchmarks encompassed in version Read more…

By Tiffany Trader

Contract Signed for New Finnish Supercomputer

December 13, 2018

After the official contract signing yesterday, configuration details were made public for the new BullSequana system that the Finnish IT Center for Science (CSC Read more…

By Tiffany Trader

Nvidia Leads Alpha MLPerf Benchmarking Round

December 12, 2018

Seven months after the launch of its AI benchmarking suite, the MLPerf consortium is releasing the first round of results based on submissions from Nvidia, Goog Read more…

By Tiffany Trader

IBM, Nvidia in AI Data Pipeline, Processing, Storage Union

December 11, 2018

IBM and Nvidia today announced a new turnkey AI solution that combines IBM Spectrum Scale scale-out file storage with Nvidia’s GPU-based DGX-1 AI server to pr Read more…

By Doug Black

Mellanox Uses Univa to Extend Silicon Design HPC Operation to Azure

December 11, 2018

Call it a corollary to Murphy’s Law: When a system is most in demand, when end users are most dependent on the system performing as required, when it’s crunch time – that’s when the system is most likely to blow up. Or make you wait in line to use it. Read more…

By Doug Black

Topology Can Help Us Find Patterns in Weather

December 6, 2018

Topology--the study of shapes--seems to be all the rage. You could even say that data has shape, and shape matters. Shapes are comfortable and familiar concepts, so it is intriguing to see that many applications are being recast to use topology. For instance, looking for weather and climate patterns. Read more…

By James Reinders

Zettascale by 2035? China Thinks So

December 6, 2018

Exascale machines (of at least a 1 exaflops peak) are anticipated to arrive by around 2020, a few years behind original predictions; and given extreme-scale performance challenges are not getting any easier, it makes sense that researchers are already looking ahead to the next big 1,000x performance goal post: zettascale computing. Read more…

By Tiffany Trader

Robust Quantum Computers Still a Decade Away, Says Nat’l Academies Report

December 5, 2018

The National Academies of Science, Engineering, and Medicine yesterday released a report – Quantum Computing: Progress and Prospects – whose optimism about Read more…

By John Russell

Revisiting the 2008 Exascale Computing Study at SC18

November 29, 2018

A report published a decade ago conveyed the results of a study aimed at determining if it were possible to achieve 1000X the computational power of the the Read more…

By Scott Gibson

Quantum Computing Will Never Work

November 27, 2018

Amid the gush of money and enthusiastic predictions being thrown at quantum computing comes a proposed cold shower in the form of an essay by physicist Mikhail Read more…

By John Russell

Cray Unveils Shasta, Lands NERSC-9 Contract

October 30, 2018

Cray revealed today the details of its next-gen supercomputing architecture, Shasta, selected to be the next flagship system at NERSC. We've known of the code-name "Shasta" since the Argonne slice of the CORAL project was announced in 2015 and although the details of that plan have changed considerably, Cray didn't slow down its timeline for Shasta. Read more…

By Tiffany Trader

IBM at Hot Chips: What’s Next for Power

August 23, 2018

With processor, memory and networking technologies all racing to fill in for an ailing Moore’s law, the era of the heterogeneous datacenter is well underway, Read more…

By Tiffany Trader

House Passes $1.275B National Quantum Initiative

September 17, 2018

Last Thursday the U.S. House of Representatives passed the National Quantum Initiative Act (NQIA) intended to accelerate quantum computing research and developm Read more…

By John Russell

Summit Supercomputer is Already Making its Mark on Science

September 20, 2018

Summit, now the fastest supercomputer in the world, is quickly making its mark in science – five of the six finalists just announced for the prestigious 2018 Read more…

By John Russell

AMD Sets Up for Epyc Epoch

November 16, 2018

It’s been a good two weeks, AMD’s Gary Silcott and Andy Parma told me on the last day of SC18 in Dallas at the restaurant where we met to discuss their show news and recent successes. Heck, it’s been a good year. Read more…

By Tiffany Trader

US Leads Supercomputing with #1, #2 Systems & Petascale Arm

November 12, 2018

The 31st Supercomputing Conference (SC) - commemorating 30 years since the first Supercomputing in 1988 - kicked off in Dallas yesterday, taking over the Kay Ba Read more…

By Tiffany Trader

TACC’s ‘Frontera’ Supercomputer Expands Horizon for Extreme-Scale Science

August 29, 2018

The National Science Foundation and the Texas Advanced Computing Center announced today that a new system, called Frontera, will overtake Stampede 2 as the fast Read more…

By Tiffany Trader

Leading Solution Providers

SC 18 Virtual Booth Video Tour

Advania @ SC18 AMD @ SC18
ASRock Rack @ SC18
DDN Storage @ SC18
HPE @ SC18
IBM @ SC18
Lenovo @ SC18 Mellanox Technologies @ SC18
NVIDIA @ SC18
One Stop Systems @ SC18
Oracle @ SC18 Panasas @ SC18
Supermicro @ SC18 SUSE @ SC18 TYAN @ SC18
Verne Global @ SC18

HPE No. 1, IBM Surges, in ‘Bucking Bronco’ High Performance Server Market

September 27, 2018

Riding healthy U.S. and global economies, strong demand for AI-capable hardware and other tailwind trends, the high performance computing server market jumped 28 percent in the second quarter 2018 to $3.7 billion, up from $2.9 billion for the same period last year, according to industry analyst firm Hyperion Research. Read more…

By Doug Black

Contract Signed for New Finnish Supercomputer

December 13, 2018

After the official contract signing yesterday, configuration details were made public for the new BullSequana system that the Finnish IT Center for Science (CSC Read more…

By Tiffany Trader

Nvidia’s Jensen Huang Delivers Vision for the New HPC

November 14, 2018

For nearly two hours on Monday at SC18, Jensen Huang, CEO of Nvidia, presented his expansive view of the future of HPC (and computing in general) as only he can do. Animated. Backstopped by a stream of data charts, product photos, and even a beautiful image of supernovae... Read more…

By John Russell

Germany Celebrates Launch of Two Fastest Supercomputers

September 26, 2018

The new high-performance computer SuperMUC-NG at the Leibniz Supercomputing Center (LRZ) in Garching is the fastest computer in Germany and one of the fastest i Read more…

By Tiffany Trader

Houston to Field Massive, ‘Geophysically Configured’ Cloud Supercomputer

October 11, 2018

Based on some news stories out today, one might get the impression that the next system to crack number one on the Top500 would be an industrial oil and gas mon Read more…

By Tiffany Trader

Intel Confirms 48-Core Cascade Lake-AP for 2019

November 4, 2018

As part of the run-up to SC18, taking place in Dallas next week (Nov. 11-16), Intel is doling out info on its next-gen Cascade Lake family of Xeon processors, specifically the “Advanced Processor” version (Cascade Lake-AP), architected for high-performance computing, artificial intelligence and infrastructure-as-a-service workloads. Read more…

By Tiffany Trader

Google Releases Machine Learning “What-If” Analysis Tool

September 12, 2018

Training machine learning models has long been time-consuming process. Yesterday, Google released a “What-If Tool” for probing how data point changes affect a model’s prediction. The new tool is being launched as a new feature of the open source TensorBoard web application... Read more…

By John Russell

The Convergence of Big Data and Extreme-Scale HPC

August 31, 2018

As we are heading towards extreme-scale HPC coupled with data intensive analytics like machine learning, the necessary integration of big data and HPC is a curr Read more…

By Rob Farber

  • arrow
  • Click Here for More Headlines
  • arrow
Do NOT follow this link or you will be banned from the site!
Share This