As open source hardware gains traction, the potential for a completely open source supercomputing system becomes a compelling proposition, one that is being investigated by the International Workshop on Open Source Supercomputing (OpenSuCo). Ahead of OpenSuCo’s inaugural workshop taking place at ISC 2017 in Frankfurt, Germany, next week, HPCwire reached out to program committee members Anastasiia Butko and David Donofrio of Lawrence Berkeley National Laboratory to learn more about the effort’s activities and vision.

HPCwire: Please introduce “OpenSuCo” — what are your goals and objectives?

OpenSuCo: As we approach the end of MOSFET scaling, the HPC community needs a way to continue performance scaling. One way of providing that scaling is by providing more specialized architectures tailored for specific applications. In order to make possible the specification and verification of these new architectures, more rapid prototyping methods need to be explored. At the same time, these new architectures need software stacks and programming models to be able to actually use these new designs.

There has been a consistent march toward open source for each of these components. At the node hardware level, Facebook has launched the Open Compute Project; Intel has launched OpenHPC, which provides software tools to manage HPC systems. However, each of these efforts use closed source components in their final version. We present OpenSuCo: a workshop for exploring and collaborating on building an HPC system using open-source hardware and system software IP (intellectual property).

The goal of this workshop is to engage the HPC community and explore open-source solutions for constructing an HPC system – from silicon to applications.

Figure illustrates the progress in open source software and hardware

HPCwire: We’ve seen significant momentum for open source silicon in the last few years, with RISC-V and Open Compute Project for example, what is the supercomputing perspective on this?

OpenSuCo: Hardware specialization, specifically the creation of Systems-On-Chip (SoCs), offers a method to create cost-effective HPC architectures from off-the-shelf components. However, effectively tapping the advantages provided by SoC specialization requires the use of expensive and often closed source tools. Furthermore, the building blocks used to create the SoC may be closed source, limiting customization. This often leaves SoC design methodologies outside the reach of many academics and DOE researchers. The case for specialized accelerators can also be made from an economic sense as, in contrast to historical trends, the energy consumed per transistor has been holding steady, while the cost (in dollars) per transistor has been steadily decreasing, implying that we will soon be able to pack more transistors into a given area than can be simultaneously operated.

From an economic standpoint, we are witnessing an explosion of highly cost-sensitive and application-specific IoT (internet of things) devices. The developers of these devices face a stark choice: spend millions on a commercial license for processors and other IP or face the significant risk and cost (in both development time and dollars) of developing custom hardware. Similar parallels can be drawn to the low-volume and rapid design needs found in many scientific and government applications. By developing a low cost and robust path to the generation of specialized hardware, we can support the development and deployment of application-tailored processors across many DOE mission areas.

The design methodologies traditionally focused for use in these cost sensitive design flows can be applied to high-end computing due to the emergence of embedded IP offering HPC-centric capabilities, such as double-precision floating point, 64-bit address capability, and options for high performance I/O and memory interfaces. The SoC approach, coupled with highly accessible open source flows, will allow chip designers to include only features they want, excluding those not utilized by mainstream HPC systems. By pushing customization into the chip, we can create customization that is not feasible with today’s commodity board-level computing system design.

HPCwire: Despite pervasive support in tech circles not everyone is convinced of the merits of open source, what is the case for open source in high performance computing?

OpenSuCo: While many commercial tools provide technology to customize a processor or system given a static baseline, they generally provide only proprietary solutions that both restrict the level of customization that can be applied, as well as increase the cost of production. This cost is of greatest importance to low-volume or highly specialized markets, such as those found in the scientific, research, and defense applications, as large volume customers can absorb this NRE as part of their overall production. As an alternative to closed source hardware flows, open source hardware has been growing in popularity in recent years and mirrors the rise of Linux and open source software in the 1990s and early 2000s. We put forth that Open Source Hardware will drive the next wave of innovation for hardware IP.

In contrast to closed-source hardware IP and flows, a completely open framework and flow enable extreme customization and drive cost for initial development to virtually zero. Going further, by leveraging community-supported and maintained technology, it is possible to also incorporate all of the supporting software infrastructure, compilers, debuggers, etc. that work with open source processor designs. A community-led effort also creates a support community that replaces what is typically found with commercial products and leads to more robust implementations as a greater number of users are testing and working with designs. Finally, for security purposes, any closed-source design carries an inherent risk in the inability to truly inspect all aspects of its operation. Open source hardware allows the user to inspect all aspects of its design for a thorough review of its security.

HPCwire: Even with the advances in open source hardware, a completely open source supercomputing system seems ambitious at this point. Can you speak to the reality of this goal in the context of the challenges and community support?

OpenSuCo: We agree that building a complete open-source HPC system is a daunting task, however, a system composed of an increased number of open source components is an excellent way to increase technological diversity and spur greater innovation.

The rapid growth and adoption of the RISC-V ISA is an excellent example of how a community can produce a complete and robust software toolchain in a relatively short time. While largely used in IoT devices at the moment, there are multiple efforts to extend the reach of RISC-V – in both implementations and functionality, into the HPC space.

HPCwire: What is needed on the software side to make this vision come together?

OpenSuCo: The needs and challenges of an open source-based supercomputer are not any greater than that of a traditional “closed” system. Most future systems will need to face the continuing demands of increased parallelism, shifting Flop-to-Byte ratios and an increase in the quantity and variety of accelerators. An open system may possess greater transparency and a larger user community allowing more effective and distributed development. Regardless, continued collaboration between software and hardware developers will be necessary to create the required community to support this effort. As part of the OpenSuCo workshop we hope to engage and bring together a diverse community of software and hardware architects willing to engage on the possibility of realizing this vision.

HPCwire: You’re holding a half-day workshop at ISC 2017 in Frankfurt on June 22. What is on the agenda and who should attend?

OpenSuCo: The ISC 2017 workshop agenda consists of three technical tracks:

Hardware Track

Sven Karlsson and Pascal Schleuniger (Danmarks Tekniske Universitet)

Kurt Keville (Massachusetts Institute of Technology)\Anne Elster (Norwegian University of Science and Technology)

Software Track

Hiroaki Kataoka and Ryos Suzuki

Anastasiia Butko (Berkeley Lab)

Xavier Teurel (Barcellona Supercomputing Center)

Collaboration Track

Bill Nitzberg (Altair Engineering, Inc.)

Jens Breitbart (Robert Bosch GmbH)

Antonio Peña (Barcelona Supercomputing Center)

Keynote Speaker: Alex Bradbury (University of Cambridge)

The complete agenda of the event can be found online at http://www.opensuco.community/2017/05/24/isc17-agenda/.

While many of the emerging technologies and opportunities surround the rise of open-source hardware, we would like to invite all members of the HPC community to participate in a true co-design effort in building a complete HPC system.

HPCwire: You’ll also be holding a workshop at SC17. You’ve put out a call for papers. How else can people get involved in OpenSuCo activities?

OpenSuCo: While we have long advocated for innovative and open source systems for the HPC community, we are just beginning to tackle this comprehensive solution and cannot do it alone. We welcome collaborators to help build the next generation of HPC software and hardware design flows.