Four companies engaged in a cage fight for leadership in the emerging HPC market of the 2020s are, despite deep differences in some areas, in violent agreement on at least one thing: the power consumption and latency penalties of data movement is Public Enemy No. 1. If we are to realize the promise of exascale computing for AI, data analytics and HPC, advanced scale systems must be rearchitected in ways that, above all, get data closer to compute – though precisely how to do that is a matter of major contention.
Technology strategists from Intel, Nvidia, HPE and Mellanox gathered last week at the Rocky Mountain Advanced Computing Consortium Symposium for a debate on “The Future of HPC Architecture.” Moderated by Tiffany Trader, managing editor of HPCwire, and Thomas Hauser, director of Research Computing at the University of Colorado Boulder, the panelists described their companies’ strategies for enabling exascale to become a practical, accessible reality (incidentally, IBM was invited to participate but declined).
Each of the four agrees that achieving exascale will require radical enhancements in compute capabilities. Each of the four is captivated by an architectural vision that places data, and reduction in data movement latency, at the center of the compute universe.
This means more than just putting more data into memory of increasingly gigantic capacity (we’ve heard talk of memory technology that will hold decades of data). That’s an important part of data centric computing but not all of it. It’s also about architectural schemes that shorten the connections between storage, memory and compute – whether by integrating memory and interconnect functions within a multi-capability processor (Intel’s Scalable System Framework), or by distributing compute to wherever data is located in the compute ecosystem – whether it’s in memory, in storage, in the network, at the edge.
This is a critical part of the strategy for deliveringe exascale systems that will power the increasingly powerful forms of AI to come. AI is candy for technology strategists at the upper echelons of business, scientific research, national defense and government, and the four technology companies represented at the RMACC panel (along with hundreds of other vendors) are the confectioners determined to deliver it.
Of course, how that architecture is cobbled together will be the key technology battleground of the coming decade. It’s all in the details. There are many ideas of dispersing and parallelizing computing power via architectural schemes, though not necessarily lots of agreement. Looked at one way, Intel seems to be moving toward a camp of its own under the umbrella of its tightly integrated Scalable Systems Framework. In another camp is Nvidia, HPE and Mellanox, where compute has vacated the center and is distributed throughout the system, wherever data resides.
“Distributed computing anywhere data lives is going to be the key to the future,” said Jerry Lotto, director HPC and technical computing at Mellanox. In response to this definitive statement, HPE’s Mike Vildibill, VP, Advanced Technologies Group, joked “Well, I’m trying desperately to have a different opinion from my colleagues….”
A central theme of the discussion, one universally agreed upon, was not just how to achieve exascale computing but how to make it relevant, accessible and practical for a broad array of workloads throughout public and private sector elements of the HPC community. The difficulties of scaling the exascale summit are immense.
Let’s consider power consumption. Vildibill put it into perspective by saying that if each system on the list of the world’s Top500 supercomputers is considered a node, the cumulative compute power of that system is roughly an exaflop of peak performance – from a system that consumes more than 650 megawatts of power (the output of a large nuclear power plant).
Clearly, greater efficiencies will have to be made if an exascale system is delivered in the 2022-23 timeframe with a footprint that fits into a reasonably sized data center that consumes 20-30MW. “That requirement alone is fundamentally driving a lot of development we’re doing at HPE,” Vildibill said, “…driving some very significant changes in system architecture done in a way that we can maintain legacy and we can still run our favorite MPI codes, but also address how data movement occurs within large-scale systems.”
“The power analysis we’ve done – and everyone’s done it and come to pretty much the same conclusion – is that something different needs to be done in the way we compute, the way we couple computation together,” said Bill Magro, an Intel Fellow and chief technologist, high performance computing software.
Specifically addressing data movement in HPC systems, he said, “Every time you move data you incur a latency, and the further the parts are apart in the system or even in a node, you suffer that latency.”
“You need programming models and compute engines that avoid moving data,” Magro said, “you need fabrics that have very efficient protocols driven by the needs of HPC to minimize back and forth traffic, whether it be for payloads, protocols or even just guarding the integrity of the data. These are the things we’re looking at.
All of this has brought about profound change in Intel’s HPC strategy, he said. It’s part of the reason Intel now describes itself as a data-centric company.
“Intel’s history has been to drive compute up and up and up,” Magro said. “But we realized a few years ago that compute actually isn’t the hardest problem, it’s everything that’s wrapped around the compute, giving (the system) balance: memory technology, fabric, storage.
“We’re trying to approach this with a systems point of view, even though we’re not a systems company,” he said, alluding to Intel’s Scalable System Framework, “because we don’t think you can get to exascale by working on components individually.”
Marc Hamilton, VP, solutions architecture and engineering at Nvidia, said the company addresses latency problems in part via a heterogeneous architecture, called “fat nodes,” in which “you have a latency-optimized core, such as a CPU, combined with a throughput-optimized core, such as a GPU” within a single system that minimizes data movement.
“You’re always going to be able to move data faster on a piece of silicon or on a motherboard than over a network,” he said.
Mellanox’s Lotto discussed taking latency out of networks by adding intelligence and compute within them.
“Traditionally, we had CPU-centric networks,” Lotto said. “The idea was that the network was basically a passive component of a cluster, that data was going to be delivered to end points in order for computation to take place. We’re trying to move toward a more data centric model for computing by enabling network devices to actually contribute to the computational load. We can offload a lot of the computational capacity from the CPU to the network.”
He cited a raft of technologies under development by Mellanox, including SHARP, SHIELD and other products, designed with the goal reducing the latency of communications frameworks like MPI down by an order of magnitude, to 3 or 4 microseconds.
Lotto expanded on these remarks to say that while processing will go wherever data exists, there also will be “coexistence” of applications and workloads within a learning environment.
“We think exascale isn’t going to look like today’s systems in terms of usages,” he said. “It’s not just going to be simulation and modeling any more. It’s going to be simulation and modeling sitting alongside machine learning and AI, sitting alongside high performance data analytics. And not just the workloads coexisting but also interacting through workflows.”
He offered a hypothetical scenario in which a scientist is conducting real time analytics on a perishable sample, and then adjusting the scientific instrument based on data as it, in real time, comes to the scientist.
“Those are types of workloads we’re focusing on, and those have broad implications for systems architecture,” Lotto said. “Not just in terms of how they coexist and connect through resource managers, but also how we make those frameworks take advantage of the core compute and fabric that sits underneath.”
But Intel’s Magro emphasized the physical limits involved in architectural design and the choices that those limits impose on vendors.
“We all have the same fundamental limits on how large a chip we can build, and that means we’re all forced to decide how to use that real estate,” he said. “So there’s a key tension, which is if I come up with something like a dedicated Tensor engine that’s wonderful and perfect for machine learning and I dedicate an area to that, by construction I’m harming the rest of HPC. So what we need to do is find the right balance of what will benefit the most from deep integration, what will be on a motherboard and what can be at the other end of the fabric. That’s where a lot of the tension is.”