Field Programmable Gate Arrays (FPGAs) have a reputation for being difficult to program, requiring expertise in specialty languages, like Verilog or VHDL. Easing the programming burden is key to unlocking broader adoption for FPGAs and it’s a prime goal of FPGA vendors, like Intel.
Yesterday Intel, which purchased FPGA company Altera in 2015, announced a new set of software tools aimed at making FPGA programming accessible to mainstream developers. It’s all part of Intel’s strategy to boost FPGA use in the datacenter, where target workloads include high-performance computing, artificial intelligence, data and video analytics, and 5G network processing.
The three tools launched by Intel are:
· The Acceleration Stack for Intel Xeon CPU with FPGAs — enables code re-use and offers a common developer interface across all Intel FPGA datacenter products. The interface abstracts hardware specific FPGA resource details from the application developer. System-optimized reference libraries are provided for target verticals.
· The Open Programmable Acceleration Engine (OPAE) Technology — open code that is included as part of the common developer interface between the Intel Xeon processor and an accelerator, providing a lightweight, consistent API across FPGA accelerator generations and platforms. The hardware-specific FPGA resource details are abstracted from the application developer. The OPAE code is on GitHub.
· The Intel FPGA Software Development Kit (SDK) for OpenCL — supporting both Register Transfer Language (RTL) and OpenCL to allow developers to create custom accelerator functions that run on Intel FPGAs.
The aim here is to bring FPGA programming into Intel’s familiar Xeon frameworks to reduce the learning curve for software developers who are not FPGA experts. Intel has identified hardware (FPGA) acceleration as a significant enabler of HPC, AI, autonomous driving, genomics, and database acceleration.
The new software was unveiled yesterday (Sept. 4) in a blog post from Barry Davis, general manager, Accelerated Workloads Group, Intel Data Center Group. Additional details were covered during the International Conference on Field-Programmable Logic and Applications (FPL) by Intel fellow Pradeep Dubey in Ghent, Belgium, on September 5.